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1. 发明授权

US07985687B1 System and method for improving reliability in a semiconductor device 有权
标题翻译：用于提高半导体器件的可靠性的系统和方法
公开(公告)号：US07985687B1
公开(公告)日：2011-07-26
申请号：US11186969
申请日：2005-07-22
申请人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
发明人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/28273 , H01L21/28282 , H01L21/3081 , H01L21/31111 , H01L21/76232 , H01L27/11521 , H01L27/11568
摘要： A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.
摘要翻译：一种用于形成存储器件的方法包括在衬底上形成硬掩模，其中硬掩模包括形成在第一掩模层上的第一掩模层和第二掩模层。蚀刻衬底以形成沟槽。沟槽填充有场氧化物材料。使用第一蚀刻技术从存储器件剥离第二掩模层，并且使用第二蚀刻技术将第一掩模层从存储器件剥离，其中第二蚀刻技术不同于第一蚀刻技术。

2. 发明授权

US08598645B2 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US08598645B2
公开(公告)日：2013-12-03
申请号：US12910331
申请日：2010-10-22
申请人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

3. 发明授权

US07842618B2 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US07842618B2
公开(公告)日：2010-11-30
申请号：US11193409
申请日：2005-08-01
申请人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

4. 发明授权

US07679129B1 System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device 有权
标题翻译：用于改善半导体器件中的氧化物 - 氧化物 - 氧化物（ONO）耦合的系统和方法
公开(公告)号：US07679129B1
公开(公告)日：2010-03-16
申请号：US11128389
申请日：2005-05-13
申请人： Angela T. Hui , Unsoon Kim , Hiroyuki Kinoshita , Kuo-Tung Chang
发明人： Angela T. Hui , Unsoon Kim , Hiroyuki Kinoshita , Kuo-Tung Chang
IPC分类号： H01L29/94
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/66825
摘要： A memory device includes a substrate and a first dielectric layer formed over the substrate. At least two charge storage elements are formed over the first dielectric layer. The substrate and the first dielectric layer include a shallow trench filled with an oxide material. The oxide material formed in a center portion of the shallow trench is removed to provide a region with a substantially rectangular cross-section.
摘要翻译：存储器件包括衬底和形成在衬底上的第一电介质层。在第一电介质层上形成至少两个电荷存储元件。衬底和第一介电层包括填充有氧化物材料的浅沟槽。形成在浅沟槽的中心部分的氧化物材料被去除以提供具有基本上矩形横截面的区域。

5. 发明授权

US6103593A Method and system for providing a contact on a semiconductor device 失效
标题翻译：用于在半导体器件上提供接触的方法和系统
公开(公告)号：US6103593A
公开(公告)日：2000-08-15
申请号：US23836
申请日：1998-02-13
申请人： Angela T. Hui , Hung-Sheng Chen , Unsoon Kim
发明人： Angela T. Hui , Hung-Sheng Chen , Unsoon Kim
IPC分类号： H01L21/762 , H01L21/768 , H01L21/76 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76237 , H01L21/76834 , Y10S438/97
摘要： A method for providing at least one contact on a semiconductor is disclosed. The semiconductor includes a plurality of isolation structures. The method and system include providing an etch-stop layer in direct contact with the semiconductor, providing a dielectric layer over the etch-stop layer, and etching through the dielectric layer and a portion of the etch-stop layer. A portion of the semiconductor in proximity with one of the plurality of isolation structures is not exposed during the etch.
摘要翻译：公开了一种在半导体上提供至少一个接触的方法。半导体包括多个隔离结构。该方法和系统包括提供与半导体直接接触的蚀刻停止层，在蚀刻停止层上方提供介电层，以及蚀刻穿过介电层和蚀刻停止层的一部分。在蚀刻期间，与多个隔离结构之一接近的半导体的一部分不暴露。

6. 发明授权

US08759894B1 System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device 有权
标题翻译：用于减少半导体器件中的电荷存储元件之间的交叉耦合噪声的系统和方法
公开(公告)号：US08759894B1
公开(公告)日：2014-06-24
申请号：US11189765
申请日：2005-07-27
申请人： Yider Wu , Hiroyuki Ogawa , Unsoon Kim , Angela T. Hui
发明人： Yider Wu , Hiroyuki Ogawa , Unsoon Kim , Angela T. Hui
IPC分类号： H01L29/78
CPC分类号： H01L27/11524 , H01L21/28273 , H01L29/66825 , H01L29/66833
摘要： A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.
摘要翻译：提供了包括基板的存储器件。第一电介质层形成在衬底上。在衬底和第一介电层的一部分中形成隔离沟槽。在隔离沟槽的相对侧上的第一介电层上形成至少两个电荷存储元件。在所述至少两个电荷存储元件上形成第二电介质层。控制栅极层形成在第二介电层上，其中隔离沟槽具有适于减小电荷存储元件的交叉耦合噪声的宽度，并且其中至少两个电荷存储元件具有适于提供足够的栅极耦合的高度所述至少两个电荷存储元件和所述控制栅极层。

7. 发明授权

US06664191B1 Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
标题翻译：非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间
公开(公告)号：US06664191B1
公开(公告)日：2003-12-16
申请号：US09973131
申请日：2001-10-09
申请人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
发明人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
IPC分类号： H01L21302
CPC分类号： H01L27/11526 , H01L21/0337 , H01L21/0338 , H01L21/76229 , H01L21/76838 , H01L27/11531 , Y10S438/975
摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.
摘要翻译：提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。第一多晶硅层沉积在覆盖STI区域的衬底上。然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

8. 发明授权

US5981341A Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core 失效
标题翻译：用于在自对准闪存芯内隔离沟槽形成期间保护隧道氧化物的侧壁间隔物
公开(公告)号：US5981341A
公开(公告)日：1999-11-09
申请号：US986160
申请日：1997-12-05
申请人： Unsoon Kim , Yowjuang W. Liu , Yu Sun , Angela T. Hui
发明人： Unsoon Kim , Yowjuang W. Liu , Yu Sun , Angela T. Hui
IPC分类号： H01L21/762 , H01L21/8247 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/76224
摘要： A method for making a self-aligned isolated flash memory core without damaging tunnel oxide layers between memory element stacks and the silicon substrate supporting the stacks includes depositing three sidewall layers on the stacks, prior to etching isolation trenches between the stacks, to thereby shield the tunnel oxide during isolation trench etching.
摘要翻译：用于制造自对准隔离闪存芯的方法，而不损坏存储元件堆叠和支撑堆叠的硅衬底之间的隧道氧化物层，包括在蚀刻堆叠之间的隔离沟槽之前在堆叠上沉积三个侧壁层，从而屏蔽隔离沟槽蚀刻期间的隧道氧化物。

9. 发明授权

US06583009B1 Innovative narrow gate formation for floating gate flash technology 有权
标题翻译：用于浮栅闪存技术的创新窄门形成
公开(公告)号：US06583009B1
公开(公告)日：2003-06-24
申请号：US10178106
申请日：2002-06-24
申请人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
发明人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/952
摘要： The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.
摘要翻译：本发明涉及一种形成层叠栅极闪存单元的方法，包括在半导体衬底上连续形成隧道氧化物层，第一导电层，多晶硅间介质层和第二导电层。该方法还包括在第二导电层上形成牺牲层，以及图案化牺牲层以形成具有与其相关联的至少一个侧向侧壁边缘的牺牲层特征。然后在牺牲层的横向侧壁边缘上形成侧壁间隔物，其中间隔件具有与其相关联的宽度，并且去除图案化的牺牲层特征。最后，使用间隔物作为硬掩模来图案化第二导电层，多晶硅间电介质和第一导电层，并且限定堆叠栅极，其中堆叠栅极的宽度是间隔物宽度的函数。

10. 发明授权

US07301193B2 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元中低Vss电阻和减少DIBL的结构和方法
公开(公告)号：US07301193B2
公开(公告)日：2007-11-27
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

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