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1. 发明授权

US06684258B1 Stackable ring network including burst transmission of data packet 失效
标题翻译：可堆叠环网包括数据包的突发传输
公开(公告)号：US06684258B1
公开(公告)日：2004-01-27
申请号：US09547759
申请日：2000-04-12
申请人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
发明人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
IPC分类号： G06F1516
CPC分类号： H04L12/433
摘要： A stackable network unit which can form a ring with other units has a master mode in which it can place packets on the ring, so that they can be ultimately forwarded from other units, and a repeat mode in which it can make a request for transfer of mastership of the ring, inserting bits in a header of an arbitration packet. If a master unit has completed the transmission of a packet and, preferably, after the required inter-packet gap has elapsed, it has not yet received an arbitration header to permit the making of an arbitration decision it can transmit a subsequent packet. The header information of this packet indicates to the other units that this subsequent packet is part of a burst of packets and the other units should not set requests in the header of this packet because this packet would not be used for arbitration. The master unit indicates the nature of the subsequent packet by setting a sequence number in the header of the packet to distinguish it and following packets in a burst from the ‘first’ packet which is the one used to pick up requests from the units that may need to become the master unit.
摘要翻译：可以与其他单元形成环的可堆叠网络单元具有主模式，其中它可以在环上放置分组，使得它们可以最终从其他单元转发，并且可以在其中进行转移请求的重复模式在该仲裁包的头部插入位。如果主单元已经完成了分组的传输，并且优选地，在所需的分组间间隔已经过去之后，它还没有接收到仲裁报头以允许作出可以发送后续分组的仲裁决定。该分组的报头信息向其他单元指示该后续分组是分组的突发的一部分，并且其他单元不应该在该分组的报头中设置请求，因为该分组不会用于仲裁。主单元通过在分组报头中设置序列号来指示后续分组的性质，以便从“第一”分组中突发出来的分组中跟随分组，该分组是用于从可能的单元接收请求的分组需要成为主机。

2. 发明授权

US06486450B1 Method and apparatus for inducing locally elevated temperatures in an application specific integrated circuit 失效
标题翻译：用于在专用集成电路中诱发局部升高的温度的方法和装置
公开(公告)号：US06486450B1
公开(公告)日：2002-11-26
申请号：US09662114
申请日：2000-09-14
申请人： Una Quinlan , Vincent Gavin , Tadhg Creedon
发明人： Una Quinlan , Vincent Gavin , Tadhg Creedon
IPC分类号： H05B102
CPC分类号： G01R31/2877
摘要： An application specific integrated circuit includes a multiplicity of operative circuit blocks. Disposed in at least one of the blocks is a multiplicity of selectively operative heater modules for providing localised heating within the block. The heater modules may comprise cyclic redundancy code generators each coupled to respond to a system clock, and each heater module may include a system clock divider providing a multiplicity of differently divided clock signals and means for selecting a clock signal for use by the module. The invention is useful in design variable testing to produce variation with temperature of the frequency of an intermittent timing error.
摘要翻译：专用集成电路包括多个操作电路块。设置在至少一个块中的是多个选择性操作的加热器模块，用于在块内提供局部加热。加热器模块可以包括循环冗余码发生器，每个循环冗余码发生器各自耦合以响应于系统时钟，并且每个加热器模块可以包括提供多个不同分割时钟信号的系统时钟分频器和用于选择模块使用的时钟信号的装置。本发明在设计变量测试中可用于产生随间歇定时误差频率的温度变化。

3. 发明申请

US20120150527A1 STORAGE PERIPHERAL DEVICE EMULATION 审中-公开
标题翻译：存储外围设备仿真
公开(公告)号：US20120150527A1
公开(公告)日：2012-06-14
申请号：US13390787
申请日：2010-08-20
申请人： Tadhg Creedon , Vincent Gavin , Eugene McCabe
发明人： Tadhg Creedon , Vincent Gavin , Eugene McCabe
IPC分类号： G06F9/455
CPC分类号： G06F3/0632 , G06F3/0607 , G06F3/0683
摘要： An emulation system (1) comprises a programming system (2) made up of a laptop computer (2(a)) and a central server (2(b)), an interrogation station (3), and a programmable storage peripheral device (4). The system (1) links with an existing disk storage peripheral device (10) to retrieve characterisation data, and upload it to the central server (2(b)). The laptop computer (2(a)) then retrieves the characterization data and then programs the programmable device (4) to emulate the full functionality of the pre-existing computer storage peripheral (10). The device (4) is programmed by the host computer (2) to fully replicate characteristics including electrical and timing characteristics and command responses. The programmable device (4) does not have a disk drive, the only storage components being solid state non-volatile memory components, in this embodiment flash memory and volatile components including DRAM. The flash components include mostly NAND flash, but also NOR flash.
摘要翻译：仿真系统（1）包括由膝上型计算机（2（a））和中央服务器（2（b））组成的编程系统（2），询问站（3）和可编程存储外围设备 4）。系统（1）与现有的磁盘存储外围设备（10）链接以检索表征数据，并将其上传到中央服务器（2（b））。膝上型计算机（2（a））然后检索表征数据，然后对可编程设备（4）进行编程，以模拟预先存在的计算机存储外围设备（10）的全部功能。设备（4）由主计算机（2）编程，以完全复制包括电气和定时特性以及命令响应的特性。可编程器件（4）没有磁盘驱动器，唯一的存储组件是固态非易失性存储器组件，在这个实施例中，闪速存储器和包括DRAM的易失性组件。闪存组件主要包括NAND闪存，也包括NOR闪存。

4. 发明授权

US06877145B2 Automatic generation of interconnect logic components 有权
标题翻译：自动生成互连逻辑元件
公开(公告)号：US06877145B2
公开(公告)日：2005-04-05
申请号：US09919806
申请日：2001-08-02
申请人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
发明人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.
摘要翻译：自动生成片上系统的互连逻辑的程序工具基于运行核心库和需要核心之间的所有数据交换的架构，通过可能是“片外”的共享存储器进行。该架构包括用于具有连续级别的仲裁来访问存储器的数据聚合技术。

5. 发明授权

US06552590B2 Clocking scheme for ASIC 失效
标题翻译： ASIC时钟方案
公开(公告)号：US06552590B2
公开(公告)日：2003-04-22
申请号：US09879065
申请日：2001-06-13
申请人： Susan M Pratt , Vincent Gavin , Tadhg Creedon , Suzanne M Hughes , Mike Lardner , Padraic O'Reilly
发明人： Susan M Pratt , Vincent Gavin , Tadhg Creedon , Suzanne M Hughes , Mike Lardner , Padraic O'Reilly
IPC分类号： H03K300
CPC分类号： G06F5/06 , G06F1/12
摘要： A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.
摘要翻译：芯片系统的时钟方案，其中系统时钟的积分子倍数在系统时钟的奇数正边缘上具有正边沿，在偶数正边缘上具有负边沿在不同频率的块之间的数据传输由高频块的状态机，并且可以在没有弹性缓冲器和/或同步器的情况下实现。

6. 发明授权

US06718411B2 Asic system architecture including data aggregation technique 失效
标题翻译： Asic系统架构包括数据聚合技术
公开(公告)号：US06718411B2
公开(公告)日：2004-04-06
申请号：US09893659
申请日：2001-06-29
申请人： Tadhg Creedon , Vincent Gavin , Denise de Paor , Kevin J Hyland , Kevin Jennings , Derek Coburn , Mike Lardner , Suzanne M Hughes , Sean Boylan , Brendan Walsh
发明人： Tadhg Creedon , Vincent Gavin , Denise de Paor , Kevin J Hyland , Kevin Jennings , Derek Coburn , Mike Lardner , Suzanne M Hughes , Sean Boylan , Brendan Walsh
IPC分类号： G06F1336
CPC分类号： G06F17/5045
摘要： An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.
摘要翻译：一种用于芯片上系统的架构，其中功能核心具有用于与公共总线系统兼容的封装器，并且总线系统包括用于不同速度和/或总线宽度的总线事务的聚合器。

7. 发明授权

US6101554A Apparatus for controlling data flow using lookup tables to link incoming packets directly to output ports 失效
标题翻译：用于使用查找表来控制数据流的装置，以将输入的分组直接链接到输出端口
公开(公告)号：US6101554A
公开(公告)日：2000-08-08
申请号：US973177
申请日：1998-06-15
申请人： Tadhg Creedon , Anne O'Connell , Eugene O'Neill , Vincent Gavin , John Hickey , Richard Gahan , William P Sherer
发明人： Tadhg Creedon , Anne O'Connell , Eugene O'Neill , Vincent Gavin , John Hickey , Richard Gahan , William P Sherer
IPC分类号： G06F13/362 , G06F13/40 , G06F13/00
CPC分类号： G06F13/362 , G06F13/4022
摘要： Apparatus for monitoring and controlling data flow ina computer network device having a plurality of parts comprises control means for directly linking ports together on the basis of additional information stored in the control means whereby incoming packets are linked directly to an utput port to achieve high performance. The additional information is stored in one more look-up tables additional to the normal CAm with the or each table addressed by separate processing. This allows the implementation to be in hardware rather than in software.
摘要翻译： PCT No.PCT / EP96 / 02338 Sec。 371日期1998年6月15日第 102（e）1998年6月15日PCT PCT 1996年5月30日提交PCT公布。公开号WO96 / 38792 日期1996年12月5日用于在具有多个部分的计算机网络设备中监视和控制数据流的装置包括控制装置，用于基于存储在控制装置中的附加信息直接将端口连接在一起，由此输入分组直接连接到输出端口实现高性能。附加信息存储在除正常CAm之外的另外一个查找表中，其中每个表通过单独处理寻址。这允许实现在硬件而不是软件。

8. 发明授权

US09158727B2 Addressable integrated circuit and method thereof 有权
标题翻译：可寻址集成电路及其方法
公开(公告)号：US09158727B2
公开(公告)日：2015-10-13
申请号：US12771302
申请日：2010-04-30
申请人： Jeremy Gorbold , James Gibbons , Tadhg Creedon , Katherine O'Riordan , John Reidy , John Morrissey
发明人： Jeremy Gorbold , James Gibbons , Tadhg Creedon , Katherine O'Riordan , John Reidy , John Morrissey
IPC分类号： G01R19/175 , G01R19/14 , G06F3/00 , G06F3/01 , G06F13/42 , G06F12/06 , G01R31/36
CPC分类号： G06F13/4247 , G01R31/3658 , G06F12/0661
摘要： An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm.
摘要翻译：在菊花链网络中寻址集成电路的示例性方法和系统。在示例性方法中，可以将集成电路的地址初始化为预定的初始地址。集成电路可以接收包括类型标识符和地址字段的命令。基于类型标识符，可以确定命令的类型。作为决定的结果，从地址字段读取地址。读取地址可以存储在寄存器中。该地址可以被修改，并且可以被输出。在接收到数据或命令时，可以通过错误检查算法来确认包括接收到的命令中的数据的数据的完整性。

9. 发明授权

US5241632A Programmable priority arbiter 失效
标题翻译：可编程优先仲裁器
公开(公告)号：US5241632A
公开(公告)日：1993-08-31
申请号：US828026
申请日：1992-01-30
申请人： Anne O'Connell , Tadhg Creedon , Deidre A. Smith
发明人： Anne O'Connell , Tadhg Creedon , Deidre A. Smith
IPC分类号： G06F13/364
CPC分类号： G06F13/364
摘要： The present invention is directed to a programmable logic circuit used as an arbiter to control access to a shared resource, e.g. a system bus, by N devices in a computer system. The programmable arbiter according to the present invention, implements a logic design with sufficient flexibility to accommodate and selectively incorporate features of several different arbitration schemes including a straight priority scheme, a programmable arbitration, and a rotating priority arbitration scheme. In addition to these arbitration schemes, the arbiter of the present invention supports an extended programmable arbitration scheme whereby a device which is requesting access to the shared resource may be granted access to the resource even if it has used up its allocated share of bandwidth if there are no other devices requesting access to the shared resource. Furthermore, bus bandwidth may be allocated to particular device or to a group of devices at a particular priority level. In addition to providing for programmable allocation of bus bandwidth, the arbiter of the present invention permits the number of clock cycles allocated per bus window for one requesting device to be different from the number of clock cycles allocated per bus window for another device. In this manner, the size of the bus window can be designed to accommodate the individual requirements of each device permitting maximization of both the device's and the system's overall efficiency.
摘要翻译：本发明涉及用作仲裁器的可编程逻辑电路，以控制对共享资源的访问，例如，系统总线，由计算机系统中的N个设备。根据本发明的可编程仲裁器实现具有足够灵活性的逻辑设计，以容纳并选择性地并入包括直接优先方案，可编程仲裁和旋转优先权仲裁方案的若干不同仲裁方案的特征。除了这些仲裁方案之外，本发明的仲裁器还支持扩展的可编程仲裁方案，由此即使在请求对共享资源的访问的设备已经占用其分配的带宽份额的情况下，也可以授予对资源的访问权限没有其他请求访问共享资源的设备。此外，可以将总线带宽分配给特定设备或特定优先级的一组设备。除了提供总线带宽的可编程分配之外，本发明的仲裁器允许一个请求设备每总线窗口分配的时钟周期数量与另一个设备每总线窗口分配的时钟周期数不同。以这种方式，总线窗口的尺寸可以被设计为适应每个设备的个体要求，允许设备和系统的整体效率最大化。

10. 发明授权

US06587389B2 DRAM refresh command operation 失效
标题翻译： DRAM刷新命令操作
公开(公告)号：US06587389B2
公开(公告)日：2003-07-01
申请号：US09984626
申请日：2001-10-30
申请人： Denise De Paor , Tadhg Creedon
发明人： Denise De Paor , Tadhg Creedon
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/1018 , G11C7/1072
摘要： A method and apparatus for refresh command operations on an SDRAM that avoids use of refresh commands requiring all banks of the SDRAM to be idle. Burst operation establishes command sequences that include Nop command intervals. Some of these Nop intervals are used to perform operations on a bank other than the one under access for the burst that provide a refresh. ACTIVE followed by PRECHARGE commands are inserted into the command intervals addressed to a refresh address. The refresh addresses are generated externally of the SDRAM and provided to a multiplexer that sequences them with the data addresses. A secondary timer checks that required refresh has occurred and prioritizes the refresh addresses over data addresses in the multiplexer in the event that a refresh has not been completed shortly before a maximum refresh interval.
摘要翻译：一种用于SDRAM上的刷新命令操作的方法和装置，其避免使用需要SDRAM的所有存储单元的刷新命令。空行操作建立包括Nop命令间隔的命令序列。这些Nop间隔中的一些用于对提供刷新的突发的除访问之外的银行执行操作。 ACTIVE接着PRECHARGE命令被插入到寻址到刷新地址的命令间隔中。刷新地址由SDRAM的外部产生，并提供给将其与数据地址进行排序的多路复用器。如果在最大刷新间隔之前不完成刷新的情况下，辅助计时器将检查是否发生了所需的刷新，并将刷新地址优先于多路复用器中的数据地址。

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