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1. 发明授权

US06177698B1 Formation of controlled trench top isolation layers for vertical transistors 失效
标题翻译：形成用于垂直晶体管的受控沟槽顶部隔离层
公开(公告)号：US06177698B1
公开(公告)日：2001-01-23
申请号：US09461599
申请日：1999-12-15
申请人： Ulrike Gruening , Jochen Beintner , Dirk Tobben , Gill Lee , Oswald Spindler , Zvonimir Gabric
发明人： Ulrike Gruening , Jochen Beintner , Dirk Tobben , Gill Lee , Oswald Spindler , Zvonimir Gabric
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L21/02126 , H01L21/02271 , H01L21/02304 , H01L21/31612 , H01L27/10876
摘要： A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.
摘要翻译：用于控制用于半导体器件的沟槽中的隔离层厚度的方法包括以下步骤：提供在其中形成的导电材料的沟槽，在导电材料上方的沟槽的侧壁上形成衬垫，在掩埋带上沉积选择性氧化物沉积层，侧壁，选择性氧化物沉积层以比在侧壁和顶表面的衬垫上更高的速率选择性地在导电材料上生长，并且除去与导电体接触的部分之外的选择性氧化物沉积层以形成隔离层沟槽中的导电材料。还包括当晶体管形成时，通过使衬底凹陷来制造垂直晶体管以允许晶体管沟道和掩埋带外扩散之间的重叠增加的方法。还公开了一种半导体器件。

2. 发明授权

US06184091B2 Formation of controlled trench top isolation layers for vertical transistors 失效
公开(公告)号：US06184091B2
公开(公告)日：2001-02-06
申请号：US09241756
申请日：1999-02-01
申请人： Ulrike Gruening , Jochen Beintner , Dirk Tobben , Gill Lee , Oswald Spindler , Zvonimir Gabric
发明人： Ulrike Gruening , Jochen Beintner , Dirk Tobben , Gill Lee , Oswald Spindler , Zvonimir Gabric
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L21/02126 , H01L21/02271 , H01L21/02304 , H01L21/31612 , H01L27/10876
摘要： A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

3. 发明授权

US06429092B1 Collar formation by selective oxide deposition 失效
标题翻译：通过选择性氧化物沉积形成环形
公开(公告)号：US06429092B1
公开(公告)日：2002-08-06
申请号：US09596606
申请日：2000-06-19
申请人： Jochen Beintner , Alexander Michaelis , Ulrike Gruening , Oswald Spindler , Zvonimir Gabric
发明人： Jochen Beintner , Alexander Michaelis , Ulrike Gruening , Oswald Spindler , Zvonimir Gabric
IPC分类号： H01L2176
CPC分类号： H01L27/10861 , H01L21/31612 , H01L21/32 , H01L27/1087
摘要： A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench in a silicon substrate, and depositing and recessing a nitride liner in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar in the trench.
摘要翻译：根据本发明的在沟槽中形成氧化物环的方法包括在硅衬底中形成沟槽，以及在沟槽中沉积和凹陷氮化物衬垫以暴露沟槽侧壁上的硅衬底的一部分。对硅衬底的部分上的氮化物衬垫选择性地沉积氧化物。从氮化物衬垫的表面去除残余氧化物，以在沟槽中形成环。

4. 发明授权

US06759291B2 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06759291B2
公开(公告)日：2004-07-06
申请号：US10045499
申请日：2002-01-14
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

5. 发明授权

US06369419B1 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06369419B1
公开(公告)日：2002-04-09
申请号：US09603657
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L2994
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

6. 发明授权

US06204140B1 Dynamic random access memory 有权
标题翻译：动态随机存取存储器
公开(公告)号：US06204140B1
公开(公告)日：2001-03-20
申请号：US09275337
申请日：1999-03-24
申请人： Ulrike Gruening , Jochen Beintner , Scott Halle , Jack A. Mandelman , Carl J. Radens , Juergen Wittmann , Jeffrey J. Welser
发明人： Ulrike Gruening , Jochen Beintner , Scott Halle , Jack A. Mandelman , Carl J. Radens , Juergen Wittmann , Jeffrey J. Welser
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10861
摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.
摘要翻译：一种方法包括在半导体本体中形成沟槽电容器。在电容器的上部形成凹部，该凹槽在半导体本体中具有侧壁。第一材料沉积在凹槽的侧壁和底部上方。第二种材料沉积在第一种材料上。在第二材料上提供面罩。掩模具有：掩蔽区域，以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹部底部的另一部分以暴露第二材料的下面部分。第二材料的暴露的下部部分的部分是选择性地去除，同时留下基本未蚀刻的暴露的第一材料的下部。选择性地去除半导体主体的第一材料和下部的暴露部分。隔离区形成在半导体本体的去除部分中。所述掩模设置在所述第二材料上方，具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域，以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分，第二材料的部分。在半导体本体的暴露的下部设置蚀刻，以在半导体本体中形成浅沟槽。在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。通过这种方法，允许更大的掩模不对准公差。

7. 发明授权

US06323103B1 Method for fabricating transistors 有权
标题翻译：晶体管制造方法
公开(公告)号：US06323103B1
公开(公告)日：2001-11-27
申请号：US09175267
申请日：1998-10-20
申请人： Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
发明人： Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
IPC分类号： H01L218238
CPC分类号： H01L21/823878 , H01L21/762
摘要： A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.
摘要翻译：提供了一种用于在半导体主体的不同电隔离有源区中制造第一和第二MOSFET晶体管的方法，每个晶体管具有多个层。第一栅极氧化物层和第一多晶硅层沉积在半导体主体上方的有源区域上。在所述第一栅极氧化物和多晶硅层和所述半导体本体中蚀刻沟槽以描绘第一和第二有源区，从而形成与第一有源区共同延伸的第一划定的栅极氧化物层和多晶硅层。材料沉积在所述沟槽中以形成有源区隔离，所述有源区隔离在所述半导体本体上方具有顶表面。然后在所述第一和第二有源区上形成掩模层，并且去除其选择性部分以暴露所述第二有源区。屏蔽层和有源区隔离一起形成掩模，其限定与第二有源区域共同延伸的开口，其中限定所述开口的有源区隔离。通过开口的材料形成第二栅氧化层和第二多晶层，这种第二层和第二多晶层与第二有源区共同延伸。第一晶体管，其具有第一划定的栅极氧化物和多晶层作为第一晶体管的多个层和第二晶体管的一对，其中第二栅极氧化物层和第二多晶层作为一对多个层的第二晶体管。

8. 发明授权

US06265742B1 Memory cell structure and fabrication 失效
标题翻译：存储单元结构和制造
公开(公告)号：US06265742B1
公开(公告)日：2001-07-24
申请号：US09317662
申请日：1999-05-24
申请人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
发明人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.
摘要翻译：通过首先形成由晶片的主体部分隔开的一对垂直沟槽，在硅晶片的单晶体部分中形成用于DRAM中的一对存储单元。在每个沟槽的壁之上形成电介质层之后，沟槽各自填充有多晶硅。通过一对凹陷形成和凹陷填充步骤，在每个沟槽的顶部形成有与中间体部分外延生长的硅区域。使每个外延区域用作在沟槽的下多晶硅填充物中具有其漏极的单独晶体管的主体，并且其源于在两个外延区域之间的单晶体体中间。每个沟槽的较低多晶硅填充物也用作每个电池的电容器的存储节点，其体积用作电容器的另一个板。

9. 发明授权

US6093614A Memory cell structure and fabrication 失效
标题翻译：存储单元结构和制造
公开(公告)号：US6093614A
公开(公告)日：2000-07-25
申请号：US34519
申请日：1998-03-04
申请人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
发明人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.
摘要翻译：通过首先形成由晶片的主体部分隔开的一对垂直沟槽，在硅晶片的单晶体部分中形成用于DRAM中的一对存储单元。在每个沟槽的壁之上形成电介质层之后，沟槽各自填充有多晶硅。通过一对凹陷形成和凹陷填充步骤，在每个沟槽的顶部形成有与中间体部分外延生长的硅区域。使每个外延区域用作在沟槽的下多晶硅填充物中具有其漏极的单独晶体管的主体，并且其源于在两个外延区域之间的单晶体体中间。每个沟槽的较低多晶硅填充物也用作每个电池的电容器的存储节点，其体积用作电容器的另一个板。

10. 发明授权

US6013937A Buffer layer for improving control of layer thickness 失效
标题翻译：缓冲层，用于改善层厚度的控制
公开(公告)号：US6013937A
公开(公告)日：2000-01-11
申请号：US938196
申请日：1997-09-26
申请人： Jochen Beintner , Ulrike Gruening , Carl Radens
发明人： Jochen Beintner , Ulrike Gruening , Carl Radens
IPC分类号： H01L21/76 , H01L21/308 , H01L21/31 , H01L21/316 , H01L21/318 , H01L21/763 , H01L21/8242 , H01L27/108 , H01L29/00 , H01L21/336 , H01L21/469 , H01L29/06
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/31 , H01L21/763 , H01L27/10867 , Y10S438/97
摘要： A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.
摘要翻译：设置在半导体衬底102上的衬垫层和布置在焊盘层内的缓冲层108，使得衬垫层被分为缓冲层下面的介电层106和缓冲层上方的掩模层110。在半导体芯片上形成具有均匀平坦度和厚度的层的方法包括以下步骤：提供具有形成在其上的热垫106的衬底，在热衬垫上形成电介质层106，在电介质层上形成缓冲层108，其中，缓冲层由与电介质层不同的材料制成，并在缓冲层上形成掩模层110，其中缓冲层由与掩模层不同的材料制成。

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