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1. 发明授权

US6133130A Method for fabricating an embedded dynamic random access memory using self-aligned silicide technology 有权
标题翻译：使用自对准硅化物技术制造嵌入式动态随机存取存储器的方法
公开(公告)号：US6133130A
公开(公告)日：2000-10-17
申请号：US181530
申请日：1998-10-28
申请人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
发明人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
IPC分类号： H01L21/285 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/10873 , H01L21/28518 , H01L21/823443 , H01L27/10894 , H01L29/665
摘要： A method includes a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM). On a silicon wafer, a first MOS transistor is formed in a logic device region, and second MOS transistor is formed in a memory device region. The improved method includes forming an insulating layer over the substrate at least covering the first (second) MOS transistor. A top portion of the insulating layer is removed to expose only a top portion of the first (second) gate structure. A portion of the insulating layer covering the first MOS transistor is removed to expose the first MOS transistor. Using the remaining insulating layer on the second MOS transistor as a mask, the Salicide fabrication process is performed to form a self-aligned silicide layer on the first interchangeable source/drain region, and the exposed top surface of the first (second) polysilicon gate structure.
摘要翻译：一种方法包括在嵌入式动态随机存取存储器（DRAM）的制造中的自对准硅化物（Salicide）技术。在硅晶片上，第一MOS晶体管形成在逻辑器件区域中，第二MOS晶体管形成在存储器件区域中。改进的方法包括在衬底上形成至少覆盖第一（第二）MOS晶体管的绝缘层。去除绝缘层的顶部以仅露出第一（第二）栅极结构的顶部。覆盖第一MOS晶体管的绝缘层的一部分被去除以暴露第一MOS晶体管。使用第二MOS晶体管上的剩余绝缘层作为掩模，执行自对准硅化物制造工艺以在第一可互换源极/漏极区上形成自对准硅化物层，并且第一（第二）多晶硅栅极的暴露的顶表面结构体。

2. 发明授权

US06187674B1 Manufacturing method capable of preventing corrosion and contamination of MOS gate 失效
标题翻译：能够防止MOS栅的腐蚀和污染的制造方法
公开(公告)号：US06187674B1
公开(公告)日：2001-02-13
申请号：US09208605
申请日：1998-12-08
申请人： Tung-Po Chen , Yung-Chang Lin , Keh-Ching Huang , Jacob Chen
发明人： Tung-Po Chen , Yung-Chang Lin , Keh-Ching Huang , Jacob Chen
IPC分类号： H01L2144
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28247 , H01L29/4941
摘要： A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.
摘要翻译： MOS门制造操作能够防止酸腐蚀和车站污染。该制造方法包括以下步骤：在硅衬底上顺序地形成多晶硅层，阻挡层，硅化物层和覆盖层，然后蚀刻以形成栅极结构。接下来，进行快速热处理以在阻挡层的暴露的侧壁上形成氧化物层。最后，通过在栅极的每一侧上形成具有轻掺杂漏极结构的源极/漏极区域来清洁衬底。薄氧化物层能够保护阻挡层免受酸腐蚀，而不会导致栅极导电性的任何明显增加。

3. 发明授权

US06225155B1 Method of forming salicide in embedded dynamic random access memory 失效
标题翻译：嵌入式动态随机存取存储器中形成自杀人的方法
公开(公告)号：US06225155B1
公开(公告)日：2001-05-01
申请号：US09208602
申请日：1998-12-08
申请人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
发明人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
IPC分类号： H01L218234
CPC分类号： H01L27/10894 , H01L21/823814 , H01L21/823835 , H01L27/10873
摘要： In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.
摘要翻译：在嵌入式动态随机存取存储器中形成硅化物层的方法中，在对源极/漏极区域进行退火处理之后，在衬底上顺序地形成薄氧化物层，氮化硅层和厚氧化物层。逻辑区域中的栅极和源极/漏极区域上的绝缘层以及存储区域中的栅极。在上述三个区域上形成硅化物层。自对准层的形成可以降低三个区域的电阻，提高速度，并且可以避免在存储区域的源极/漏极区域上形成自对准硅化物层。因此，可以避免电流泄漏。此外，在源极/漏极区域的退火处理之后进行形成硅化物层的步骤，因此也可以解决多晶硅层中的杂质的热稳定性和相互扩散问题。

4. 发明授权

US06197672B1 Method for forming polycide dual gate 失效
标题翻译：多晶硅双栅极的形成方法
公开(公告)号：US06197672B1
公开(公告)日：2001-03-06
申请号：US09208271
申请日：1998-12-08
申请人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
发明人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
IPC分类号： H01L213205
CPC分类号： H01L21/28061 , H01L29/4941
摘要： A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an &agr;-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.
摘要翻译：一种形成双重多晶硅栅极的方法。提供具有隔离结构的衬底，在衬底上沉积多晶硅层（或α-Si层），将N型和P型掺杂剂注入到多晶硅层中以形成具有N- 型门和P型门。执行退火步骤以恢复多晶硅层的表面晶体结构，在掺杂多晶硅层上沉积氧化物层，并且在氧化物层上形成硅化物层。硅化物层，氧化物层和多晶硅层被定义为形成多晶硅栅极，在衬底的栅极旁边形成轻掺杂的源极/漏极区域。在栅极的侧壁上形成间隔物，并且在衬底中的间隔物旁边形成重掺杂的源/漏区。

5. 发明授权

US06177334B1 Manufacturing method capable of preventing corrosion of metal oxide semiconductor 有权
标题翻译：能够防止金属氧化物半导体的腐蚀的制造方法
公开(公告)号：US06177334B1
公开(公告)日：2001-01-23
申请号：US09203024
申请日：1998-12-01
申请人： Tung-Po Chen , Yung-Chang Lin , Jacob Chen
发明人： Tung-Po Chen , Yung-Chang Lin , Jacob Chen
IPC分类号： H01L2120
CPC分类号： H01L21/02071 , H01L21/28061 , H01L21/28247 , H01L21/32137 , H01L29/6659
摘要： A manufacturing method is capable of preventing corrosion of a metal oxide semiconductor. The manufacturing method sequentially forms a polysilicon layer, a silicide layer and a top cap layer over a substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the silicide layer. Finally, the substrate is cleaned, and then of a source/drain region having a lightly doped drain structure is formed on each side of the gate.
摘要翻译：制造方法能够防止金属氧化物半导体的腐蚀。制造方法在衬底上顺序地形成多晶硅层，硅化物层和顶盖层，然后蚀刻以形成栅极结构。接下来，进行快速热处理以在硅化物层的暴露的侧壁上形成氧化物层。最后，清洗衬底，然后在栅极的每一侧形成具有轻掺杂漏极结构的源/漏区。

6. 发明授权

US06316311B1 Method of forming borderless contact 失效
标题翻译：形成无边界接触的方法
公开(公告)号：US06316311B1
公开(公告)日：2001-11-13
申请号：US09203036
申请日：1998-12-01
申请人： Tung-Po Chen , Tong-Yu Chen , Keh-Ching Huang , Jacob Chen
发明人： Tung-Po Chen , Tong-Yu Chen , Keh-Ching Huang , Jacob Chen
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L27/10873 , H01L27/10894
摘要： A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.
摘要翻译：提供了形成无边界接触的方法。提供基板。衬底至少具有逻辑区域和存储区域。在逻辑区域上形成MOS晶体管和STI结构。 MOS晶体管包括栅极，源极/漏极区域和栅极上的帽绝缘层。在衬底上形成蚀刻停止层以覆盖MSO晶体管和STI结构。在蚀刻停止层中形成介电层。根据第一掩模层的图案，介电层，蚀刻停止层和盖绝缘层被部分去除以形成第一开口。第一个开放暴露了大门。根据第二掩模层的图案，电介质层和蚀刻停止层被部分地去除以形成在电介质层中暴露源/漏区的开口。

7. 发明授权

US06200848B1 Method of fabricating self-aligned contact in embedded DRAM 有权
标题翻译：嵌入式DRAM中自对准接触的制作方法
公开(公告)号：US06200848B1
公开(公告)日：2001-03-13
申请号：US09208612
申请日：1998-12-08
申请人： Yung-Chang Lin , Jacob Chen
发明人： Yung-Chang Lin , Jacob Chen
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10894
摘要： A method of fabricating a self-aligned contact. A substrate is defined as a memory region and a logic region. Metal oxide semiconductors and source/drain regions are respectively formed in the memory region and in the logic region. A defined dielectric layer is formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region until the source/drain regions are exposed. Silicide layers are formed over the contact holes. Portions of the silicide layer extend to surface of the dielectric layer neighboring the contact holes. A defined inter-layer dielectric layer is formed over the substrate. Vias are respectively formed in the memory region and in the logic region. The vias are filled with conductive layers. The self-aligned contact is formed.
摘要翻译：一种制造自对准接触的方法。衬底被定义为存储区域和逻辑区域。金属氧化物半导体和源极/漏极区域分别形成在存储区域和逻辑区域中。在衬底上形成限定的电介质层。接触孔分别形成在存储区域和逻辑区域中，直到源极/漏极区域露出。硅化物层形成在接触孔上。硅化物层的一部分延伸到与接触孔相邻的电介质层的表面。在衬底上形成限定的层间电介质层。通孔分别形成在存储器区域和逻辑区域中。通孔填充有导电层。形成自对准接触。

8. 发明授权

US06297133B1 Method of fabricating well 失效
标题翻译：制作方法
公开(公告)号：US06297133B1
公开(公告)日：2001-10-02
申请号：US09123737
申请日：1998-07-28
申请人： Jacob Chen , Tz-Guei Jung
发明人： Jacob Chen , Tz-Guei Jung
IPC分类号： H01L21265
CPC分类号： H01L21/823493 , H01L27/10844 , H01L27/10894
摘要： A method of manufacturing wells comprises the step of providing a p-type substrate and then sequentially forming a p-well and n-well with low dosage in the p-type substrate. Thereafter, energy is used to dope n-type ions into the p-well. The triple well formed in the present invention has low dosage ions, hence the DRAM formed on the triple well in subsequent process can have a faster refresh time.
摘要翻译：制造井的方法包括提供p型衬底，然后在p型衬底中以低剂量顺序形成p阱和n-阱的步骤。此后，使用能量将n型离子掺杂到p阱中。在本发明中形成的三重阱具有低剂量离子，因此在后续工艺中形成在三阱上的DRAM可以具有更快的刷新时间。

9. 发明授权

US06177297B1 Method of forming metallic fuse demanding lower laser power for circuit repair 有权
标题翻译：形成金属保险丝的方法，要求较低的激光功率进行电路修复
公开(公告)号：US06177297B1
公开(公告)日：2001-01-23
申请号：US09227953
申请日：1999-01-11
申请人： Jacob Chen , Wen-Jeng Lin
发明人： Jacob Chen , Wen-Jeng Lin
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： An improved formation method produces a metallic fuse capable of lowering the laser power needed for carrying out circuit repair. The method includes forming a metallic fuse when the penultimate metallic layer is formed. Since the metallic fuse is not too far away from the top surface, the power of the laser beam necessary for repairing the circuit can be moderate. Furthermore, the laser beam is more focused because it travels a shorter distance to reach the fuse, thereby avoiding unnecessary dispersion through intermediate material. Moreover, since the metallic fuse itself is not too thick, only a low-power laser beam is needed to melt the metallic fuse.
摘要翻译：改进的形成方法产生能够降低执行电路修复所需的激光功率的金属保险丝。该方法包括在倒数第二个金属层形成时形成金属熔丝。由于金属保险丝距离顶表面不是太远，修理电路所需的激光束的功率可以适中。此外，激光束由于其行进较短的距离而到达保险丝而被聚焦，从而避免了通过中间材料的不必要的分散。此外，由于金属熔断器本身不太厚，所以仅需要低功率激光束来熔化金属熔断器。

10. 发明授权

US5522532A Single-shooting/continuous-shooting control switch for penumatic nail guns 失效
标题翻译：单枪/连续拍摄控制开关，用于阴茎指甲枪
公开(公告)号：US5522532A
公开(公告)日：1996-06-04
申请号：US403616
申请日：1995-03-14
申请人： Jacob Chen
发明人： Jacob Chen
IPC分类号： B25C1/00 , B25C1/04
CPC分类号： B25C1/008 , B25C1/04
摘要： A single-shooting/continuous-shooting control switch installed in a pneumatic nail gun for controlling the firing of nails, the control switch including a first valve seat connected to a pneumatic pressure source, a second valve seat connected between the first valve seat and the firing pin of the pneumatic nail gun, a first valve rod moved by the trigger of the pneumatic nail gun to control the air passage between the first air valve seat and the second air valve seat, a second valve rod moved by the trigger of the pneumatic nail gun to control the air passage between the second air valve seat and the firing pin, and a stop block turned about the first valve rod between between a first position for letting the first valve rod be lifted by the trigger to stop the passage between the first air passage and the second air passage for a single-shooting operation, and a second position to stop the trigger from lifting the first valve rod for letting pneumatic pressure be continuosuly drawn from the first air valve seat into the second air valve seat for a continuous shooting operation.
摘要翻译：安装在气枪式喷枪中用于控制指甲点火的单次/连续拍摄控制开关，该控制开关包括连接到气动压力源的第一阀座，连接在第一阀座与第二阀座之间的第二阀座气动钉枪的撞针，由气动钉枪触发器移动的第一阀杆，以控制第一空气阀座与第二空气阀座之间的空气通道，由气动扳机触发的第二阀杆用于控制第二空气阀座和撞击销之间的空气通道的止动块，以及在第一位置之间转动第一阀杆的止动块，用于使第一阀杆由触发器提升以阻止第二阀杆之间的通道第一空气通道和第二空气通道用于单次拍摄操作，并且第二位置用于停止触发器提升第一阀杆以使气动压力被连续抽出从第一空气阀座进入第二空气阀座进行连续拍摄操作。

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