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1. 发明授权

US06316311B1 Method of forming borderless contact 失效
标题翻译：形成无边界接触的方法
公开(公告)号：US06316311B1
公开(公告)日：2001-11-13
申请号：US09203036
申请日：1998-12-01
申请人： Tung-Po Chen , Tong-Yu Chen , Keh-Ching Huang , Jacob Chen
发明人： Tung-Po Chen , Tong-Yu Chen , Keh-Ching Huang , Jacob Chen
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L27/10873 , H01L27/10894
摘要： A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.
摘要翻译：提供了形成无边界接触的方法。提供基板。衬底至少具有逻辑区域和存储区域。在逻辑区域上形成MOS晶体管和STI结构。 MOS晶体管包括栅极，源极/漏极区域和栅极上的帽绝缘层。在衬底上形成蚀刻停止层以覆盖MSO晶体管和STI结构。在蚀刻停止层中形成介电层。根据第一掩模层的图案，介电层，蚀刻停止层和盖绝缘层被部分去除以形成第一开口。第一个开放暴露了大门。根据第二掩模层的图案，电介质层和蚀刻停止层被部分地去除以形成在电介质层中暴露源/漏区的开口。

2. 发明授权

US6010968A Method for forming a contact opening with multilevel etching 有权
标题翻译：用多层蚀刻形成接触孔的方法
公开(公告)号：US6010968A
公开(公告)日：2000-01-04
申请号：US220541
申请日：1998-12-24
申请人： Chan-Lon Yang , Tong-Yu Chen , Keh-Ching Huang
发明人： Chan-Lon Yang , Tong-Yu Chen , Keh-Ching Huang
IPC分类号： H01L21/311 , H01L21/00
CPC分类号： H01L21/31116
摘要： A multilevel contact etching method to form a contact opening is provided. The method contains using an inductively coupled plasma (ICP) etcher to produce a high plasma density condition. The plasma gas etchant is composed of C.sub.4 F.sub.8 /CH.sub.2 F.sub.2 /CO/Ar with a ratio of 3:4:12:80 so that silicon nitride can be selectively etched while the silicon and silicide are not etched. Each content ratio of the plasma gas etchant allows a variance of about 20%. Wall temperature of the ICP etcher is about 100.degree. C.-300.degree. C. A cooling system for a wafer pad is about -20.degree. C.-20.degree. C. Chamber pressure is about 5-100 mtorr. Bias power on the wafer pad is about 1000 W-3000 W. Source power of an inductance coil is about 500 W-3000 W.
摘要翻译：提供了形成接触开口的多层接触蚀刻方法。该方法包括使用电感耦合等离子体（ICP）蚀刻器来产生高等离子体密度条件。等离子体气体蚀刻剂由比例为3：4：12：80的C4F8 / CH2F2 / CO / Ar组成，以便在不蚀刻硅和硅化物的情况下，可以选择性地蚀刻氮化硅。等离子体气体蚀刻剂的每个含量比允许约20％的变化。 ICP蚀刻器的壁温为约100℃-300℃。晶片垫的冷却系统为约-20℃-20℃。室压力为约5-100mtorr。晶片垫上的偏置功率约为1000W-3000W。电感线圈的功率为约500W-3000W。

3. 发明授权

US06306757B1 Method for forming a multilevel interconnect 失效
标题翻译：用于形成多层互连的方法
公开(公告)号：US06306757B1
公开(公告)日：2001-10-23
申请号：US09323890
申请日：1999-06-02
申请人： Keh-Ching Huang , Ming-Sheng Yang , Tong-Yu Chen , Tzu-Guey Jung
发明人： Keh-Ching Huang , Ming-Sheng Yang , Tong-Yu Chen , Tzu-Guey Jung
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76841 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metallization method for forming multilevel interconnect is disclosed. The method includes firstly providing a first conductor layer on which there is a dielectric layer. A glue layer is then formed on the dielectric layer, followed by forming an opening from top surface of the glue layer to the first conductor layer. After forming a barrier layer on the glue layer and all surfaces in the opening, a second conductor is formed on the barrier layer and fills the opening. Subsequently, the second conductor layer and the barrier layer are removed until the glue layer exposes. A third conductor is defined on the glue layer and the second conductor. The product will solve the problem of high via resistivity caused by stripping solvent and etchant.
摘要翻译：公开了一种用于形成多层互连的金属化方法。该方法包括首先提供其上存在电介质层的第一导体层。然后在电介质层上形成胶层，随后从胶层的顶表面到第一导体层形成开口。在胶层和开口中的所有表面上形成阻挡层之后，在阻挡层上形成第二导体并填充开口。随后，去除第二导体层和阻挡层，直到胶层露出。第三导体被限定在胶层和第二导体上。该产品将解决由剥离溶剂和蚀刻剂引起的高电阻率的问题。

4. 发明授权

US06184147B2 Method for forming a high aspect ratio borderless contact hole 有权
标题翻译：用于形成高纵横比无边界接触孔的方法
公开(公告)号：US06184147B2
公开(公告)日：2001-02-06
申请号：US09263421
申请日：1999-03-05
申请人： Chan-Lon Yang , Tong-Yu Chen , Keh-Ching Huang
发明人： Chan-Lon Yang , Tong-Yu Chen , Keh-Ching Huang
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01J37/32082 , H01J2237/3347 , H01L21/31116 , H01L21/31144 , H01L21/76802
摘要： A method for forming a high aspect ration (HAR>4:1) borderless contact hole is described. The method forms a contact/via hole in the silicon oxide layer by performing an etching process with an etchant, C4F8/C2F6,/Ar/CO or C4F8/Ar/CO, on an etcher. The etcher includes a ring, a roof, a chiller and a chamber. The etchant used in the etching process is controlled under conditions including a C4F8 flow of about 10 to 20 sccm, a CO flow of about 1 to 100 sccm, and an Ar flow of about 100 to 500 sccm. The flow of C2F6 is about 0.5 to 1.5 times that of C4F8. The conditions of the etcher include a roof temperature of about 150 to 300° C., a chiller temperature of about −20 to 20° C., a wall temperature of about 150 to 400° C., a ring temperature of about 150 to 400° C., and a pressure within the chamber of about 4 to 50 mtorr. By controlling the chamber pressure and the deposition rate of the polymer molecules, a properly profiled contact hole is obtained.
摘要翻译：描述了形成高纵横比（HAR> 4:1）无边界接触孔的方法。该方法通过在蚀刻剂上用蚀刻剂C 4 F 8 / C 2 F 6，/ Ar / CO或C 4 F 8 / Ar / CO执行蚀刻处理来形成氧化硅层中的接触/通孔。蚀刻器包括环，屋顶，冷却器和室。在蚀刻工艺中使用的蚀刻剂在约10至20sccm的C 4 F 8流量，约1至100sccm的CO流量和约100至500sccm的Ar流量的条件下进行控制。 C2F6的流量约为C4F8的0.5〜1.5倍。蚀刻器的条件包括约150至300℃的屋顶温度，约-20至20℃的冷却器温度，约150至400℃的壁温度，约150至400℃的环境温度 400℃，室内的压力为约4至50毫托。通过控制室压力和聚合物分子的沉积速率，获得适当的异型接触孔。

5. 发明授权

US08803247B2 Fin-type field effect transistor 有权
标题翻译：鳍型场效应晶体管
公开(公告)号：US08803247B2
公开(公告)日：2014-08-12
申请号：US13326429
申请日：2011-12-15
申请人： Chih-Jung Wang , Tong-Yu Chen
发明人： Chih-Jung Wang , Tong-Yu Chen
IPC分类号： H01L27/148 , H01L29/66 , H01L29/00 , H01L27/088 , H01L21/339 , H01L21/00 , H01L21/84 , H01L21/338 , H01L21/337 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/1211 , H01L21/845
摘要： A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.
摘要翻译：提供了包括至少一个鳍式半导体结构，栅极条和栅极绝缘层的鳍式场效应晶体管。翅片型半导体结构掺杂有第一种掺杂剂并具有具有第一掺杂浓度的阻挡区和具有第二掺杂浓度的沟道区。第一掺杂浓度大于第二掺杂浓度。阻挡区域具有高度。通道区域被配置在阻塞区域之上。栅极条基本上垂直于鳍状半导体结构并且覆盖在沟道区域上方。栅极绝缘层设置在栅极条和鳍状半导体结构之间。

6. 发明授权

US07319074B2 Method of defining polysilicon patterns 有权
标题翻译：定义多晶硅图案的方法
公开(公告)号：US07319074B2
公开(公告)日：2008-01-15
申请号：US11160178
申请日：2005-06-13
申请人： Pei-Yu Chou , Tong-Yu Chen
发明人： Pei-Yu Chou , Tong-Yu Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/31138 , H01L21/32137
摘要： The present invention provides a method of defining polysilicon patterns. The method forms a polysilicon layer on a substrate, and a patterned mask on the polysilicon layer. Then, a first etching process is performed to remove a portion of the polysilicon layer not covered by the mask, thus forming a plurality of cavities in the polysilicon layer. A strip process is performed to strip the mask utilizing gases excluding O2. Finally, a second etching process is performed to remove a portion of the polysilicon layer, thus extending the plurality of cavities down to a surface of the substrate.
摘要翻译：本发明提供了一种限定多晶硅图案的方法。该方法在衬底上形成多晶硅层，并在多晶硅层上形成图案化掩模。然后，进行第一蚀刻处理以去除未被掩模覆盖的多晶硅层的一部分，从而在多晶硅层中形成多个空腔。执行条带处理以利用除O 2以外的气体剥离掩模。最后，执行第二蚀刻工艺以去除多晶硅层的一部分，从而将多个空腔向下延伸到衬底的表面。

7. 发明授权

US06972259B2 Method for forming openings in low dielectric constant material layer 有权
公开(公告)号：US06972259B2
公开(公告)日：2005-12-06
申请号：US10291911
申请日：2002-11-13
申请人： Chih-Jung Wang , Tong-Yu Chen
发明人： Chih-Jung Wang , Tong-Yu Chen
IPC分类号： H01L21/027 , H01L21/28 , H01L21/302 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L29/40
CPC分类号： H01L21/76811 , H01L21/0276 , H01L21/31144 , H01L21/76813
摘要： The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.

8. 发明授权

US06352938B2 Method of removing photoresist and reducing native oxide in dual damascene copper process 有权
标题翻译：在双镶嵌铜工艺中去除光致抗蚀剂和还原天然氧化物的方法
公开(公告)号：US06352938B2
公开(公告)日：2002-03-05
申请号：US09457561
申请日：1999-12-09
申请人： Tong-Yu Chen , Hsi-Ta Chuang , Chan-Lon Yang
发明人： Tong-Yu Chen , Hsi-Ta Chuang , Chan-Lon Yang
IPC分类号： H01L21302
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/31138 , H01L21/76838 , H01L21/76843 , H01L21/76865 , H01L21/76873 , H01L21/76879
摘要： A method of manufacturing metallic interconnects. A substrate has a copper line formed therein. An inter-metal dielectric layer is formed over the substrate and the copper line. A patterned photoresist layer is formed over the inter-metal dielectric layer. The inter-metal dielectric layer is etched to form a trench and a contact opening that exposes a portion of the copper line, wherein the contact opening is under the trench. At a low temperature and using a plasma derived from a gaseous mixture N2H2 (H2:4%)/O2, the photoresist layer is removed. Any copper oxide layer formed on the copper line in the process of removing photoresist material is reduced back to copper using gaseous N2H2 (H2:4%). A barrier layer conformal to the trench and the contact opening profile is formed. Copper is deposited to form a conformal first copper layer over the trench and the contact opening. Using the first copper layer as a seeding layer, a copper or a copperless electroplating is carried out so that a second copper layer is grown anisotropically over the first copper layer.
摘要翻译：一种制造金属互连的方法。基板上形成有铜线。在衬底和铜线之上形成金属间介电层。在金属间介电层上形成图案化的光致抗蚀剂层。蚀刻金属间电介质层以形成暴露铜线的一部分的沟槽和接触开口，其中接触开口在沟槽下方。在低温下并使用来自气态混合物N 2 H 2（H 2：4％）/ O 2）的等离子体，除去光致抗蚀剂层。在除去光致抗蚀剂材料的工艺中在铜线上形成的任何铜氧化物层都使用气态N 2 H 2（H 2：4％）还原成铜。形成与沟槽一致的阻挡层和形成接触开口轮廓。沉积铜以在沟槽和接触开口上形成共形的第一铜层。使用第一铜层作为接种层，进行铜或无铜电镀，使得第二铜层在第一铜层上各向异性地生长。

9. 发明授权

US5994233A Oxide etching method 有权
标题翻译：氧化物蚀刻法
公开(公告)号：US5994233A
公开(公告)日：1999-11-30
申请号：US172507
申请日：1998-10-14
申请人： Tong-Yu Chen , Chan-Lon Yang , Tsu-An Lin
发明人： Tong-Yu Chen , Chan-Lon Yang , Tsu-An Lin
IPC分类号： H01L21/311 , H01L21/00 , H01L21/3065
CPC分类号： H01L21/31116
摘要： An oxide etching method using low-medium density plasma includes a first etching step to pre-etch the oxide layer with low etching selectivity etchant to pre-form a contact opening and a monitoring opening. The low etching selectivity etchant can also etch the photoresist layer and the photoresist reaction residue. Then, a second etching with high etching selectivity on the oxide is performed to completely form the contact opening with a SAC property and the monitoring opening. The openings expose the substrate.
摘要翻译：使用低介质密度等离子体的氧化物蚀刻方法包括用低蚀刻选择性蚀刻剂预蚀刻氧化物层以预先形成接触开口和监测开口的第一蚀刻步骤。低蚀刻选择性蚀刻剂也可以蚀刻光致抗蚀剂层和光致抗蚀剂反应残余物。然后，执行对氧化物具有高蚀刻选择性的第二蚀刻，以完全形成具有SAC特性和监测开口的接触开口。开口露出基板。

10. 发明授权

US09105590B2 Semiconductor structure having material layers which are level with each other and manufacturing method thereof 有权
标题翻译：具有彼此平坦的材料层的半导体结构及其制造方法
公开(公告)号：US09105590B2
公开(公告)日：2015-08-11
申请号：US13206523
申请日：2011-08-10
申请人： Tong-Yu Chen
发明人： Tong-Yu Chen
IPC分类号： H01L29/06 , H01L21/3213 , H01L21/033 , H01L21/768
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/76816 , H01L21/76838
摘要： A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.
摘要翻译：在本发明中提供半导体结构。半导体结构包括基板，第一材料层和第二材料层。在衬底上限定沟槽区域。沟槽区域包括两个分开的第一区域和第二区域，其中第二区域与两个第一区域相邻并且在两个第一区域之间。第一材料层设置在沟槽区域外的衬底上。第二材料层设置在第二区域中并与第一材料层平齐。

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