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1. 发明授权

US06177297B1 Method of forming metallic fuse demanding lower laser power for circuit repair 有权
标题翻译：形成金属保险丝的方法，要求较低的激光功率进行电路修复
公开(公告)号：US06177297B1
公开(公告)日：2001-01-23
申请号：US09227953
申请日：1999-01-11
申请人： Jacob Chen , Wen-Jeng Lin
发明人： Jacob Chen , Wen-Jeng Lin
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： An improved formation method produces a metallic fuse capable of lowering the laser power needed for carrying out circuit repair. The method includes forming a metallic fuse when the penultimate metallic layer is formed. Since the metallic fuse is not too far away from the top surface, the power of the laser beam necessary for repairing the circuit can be moderate. Furthermore, the laser beam is more focused because it travels a shorter distance to reach the fuse, thereby avoiding unnecessary dispersion through intermediate material. Moreover, since the metallic fuse itself is not too thick, only a low-power laser beam is needed to melt the metallic fuse.
摘要翻译：改进的形成方法产生能够降低执行电路修复所需的激光功率的金属保险丝。该方法包括在倒数第二个金属层形成时形成金属熔丝。由于金属保险丝距离顶表面不是太远，修理电路所需的激光束的功率可以适中。此外，激光束由于其行进较短的距离而到达保险丝而被聚焦，从而避免了通过中间材料的不必要的分散。此外，由于金属熔断器本身不太厚，所以仅需要低功率激光束来熔化金属熔断器。

2. 发明授权

US06218239B1 Manufacturing method of a bottom plate 失效
标题翻译：底板的制造方法
公开(公告)号：US06218239B1
公开(公告)日：2001-04-17
申请号：US09195168
申请日：1998-11-17
申请人： Keh-Ching Huang , Wen-Jeng Lin , Tz-Guei Jung , Jacob Chen
发明人： Keh-Ching Huang , Wen-Jeng Lin , Tz-Guei Jung , Jacob Chen
IPC分类号： H01L218242
CPC分类号： H01L28/87 , H01L27/10855 , H01L28/91
摘要： The invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions. A crown-liked conductive plate is formed over an insulation oxide layer and a contact plug. The crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug. The crown-like conductive plate, served as the bottom plate for a DRAM capacitor, is composed of tungsten silicide or a combination of a tungsten nitride layer and a tungsten layer.
摘要翻译：本发明提供一种在基板上形成用于电容器的底板的制造方法，其中所述基板包括具有栅极和一对源极/漏极区域的MOS晶体管。冠状导电板形成在绝缘氧化物层和接触插塞上。冠状导电板穿透绝缘层和阻挡层，其中冠状导电板的底部电连接到接触插塞。用作DRAM电容器的底板的冠状导电板由硅化钨或氮化钨层和钨层的组合构成。

3. 发明申请

US20070298567A1 SRAM CELL STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US20070298567A1
公开(公告)日：2007-12-27
申请号：US11852185
申请日：2007-09-07
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rem-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rem-Hurng Larn
IPC分类号： H01L21/8244
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

4. 发明授权

US07157763B2 SRAM cell structure and manufacturing method thereof 有权
公开(公告)号：US07157763B2
公开(公告)日：2007-01-02
申请号：US10983140
申请日：2004-11-04
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

5. 发明申请

US20060192241A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060192241A1
公开(公告)日：2006-08-31
申请号：US11066994
申请日：2005-02-25
申请人： Tzung-Han Lee , Wen-Jeng Lin , Kuang-Pi Lee , Blue Larn
发明人： Tzung-Han Lee , Wen-Jeng Lin , Kuang-Pi Lee , Blue Larn
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/6653
摘要： A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.
摘要翻译：包括衬底，堆叠栅极结构，导电间隔物，氧化物/氮化物/氧化物层，掩埋掺杂区域，控制栅极和绝缘层的非易失性存储器。层叠的栅极结构设置在基板上。堆叠栅极结构包括栅极介电层，选择栅极和盖层。导电间隔物设置在堆叠栅结构的侧壁上。氧化物/氮化物/氧化物层设置在导电间隔物和层叠栅极结构之间以及导电间隔物和衬底之间。掩埋掺杂区域设置在层叠栅极结构的每一侧上的导电间隔物外部的衬底中。控制栅极设置在堆叠的栅极结构上并电连接到导电间隔物。绝缘层设置在掩埋掺杂层和控制栅极之间。

6. 发明申请

US20060202248A1 SRAM cell structure and manufacturing method thereof 有权
公开(公告)号：US20060202248A1
公开(公告)日：2006-09-14
申请号：US11416926
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

7. 发明申请

US20050098905A1 SRAM cell structure and manufacturing method thereof 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US20050098905A1
公开(公告)日：2005-05-12
申请号：US10983140
申请日：2004-11-04
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

8. 发明授权

US5946568A Self aligned method of fabricating a DRAM with improved capacitance 失效
标题翻译：制造具有改善电容的DRAM的自对准方法
公开(公告)号：US5946568A
公开(公告)日：1999-08-31
申请号：US649466
申请日：1996-05-17
申请人： Chia-Shun Hsiao , Wei-Jing Wen , Wen-Jeng Lin , Chung-Chih Wang
发明人： Chia-Shun Hsiao , Wei-Jing Wen , Wen-Jeng Lin , Chung-Chih Wang
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8242
CPC分类号： H01L27/10852 , H01L21/76897 , H01L28/82
摘要： A solid state memory fabrication method of DRAM chips with a self-alignment of field plate/BL isolation process includes using oxide-poly-oxide etch followed by oxidation or sidewall deposition (LPTEOS) to isolate the field plate and BL. This process uses a first etchant and a second etchant in etching the BL/N.sup.+ contact in the fabrication process. During the etch of BL/N.sup.+ contact (2C etch), a low selectivity etchant etches away Ploy-3 first. This first etchant is applied for approximately one hundred eighty seconds. And then a second etchant process is performed using a high Si selectivity etchant, which etches a way the residual oxide. The second etchant is applied for approximately ninety seconds. The exposed poly on the sidewall is isolated from the contact hole by oxidation or deposition (LPTEOS). The oxide formed on the substrate during oxidation is etched away by anisotropic etch. The self-alignment of BL/3P is thus achieved. The planar area of 2P can be increased by this method and not be limited by the overlap of 2C/3P.
摘要翻译：具有场板/ BL隔离工艺的自对准的DRAM芯片的固态存储器制造方法包括使用氧化物 - 多氧化物蚀刻，随后氧化或侧壁沉积（LPTEOS）来隔离场板和BL。该工艺在制造工艺中使用第一蚀刻剂和第二蚀刻剂来蚀刻BL / N +接触。在BL / N +接触蚀刻（2C蚀刻）期间，低选择性蚀刻剂首先蚀刻Ploy-3。该第一蚀刻剂应用大约一百八十秒。然后使用高Si选择性蚀刻剂进行第二蚀刻工艺，其蚀刻残余氧化物的方式。第二种蚀刻剂应用大约九十秒。侧壁上的暴露的聚合物通过氧化或沉积（LPTEOS）与接触孔隔离。在氧化过程中形成在衬底上的氧化物被各向异性腐蚀蚀刻掉。因此实现了BL / 3P的自对准。可以通过这种方法增加2P的平面面积，而不受2C / 3P的重叠的限制。

9. 发明授权

US07358556B2 SRAM cell structure and manufacturing method thereof 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US07358556B2
公开(公告)日：2008-04-15
申请号：US11416926
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

10. 发明授权

US06306760B1 Method of forming a self-aligned contact hole on a semiconductor wafer 失效
标题翻译：在半导体晶片上形成自对准接触孔的方法
公开(公告)号：US06306760B1
公开(公告)日：2001-10-23
申请号：US09457327
申请日：1999-12-09
申请人： Hsin-Tuei Hsu , Yuang-Chang Lin , Wen-Jeng Lin
发明人： Hsin-Tuei Hsu , Yuang-Chang Lin , Wen-Jeng Lin
IPC分类号： H01L21265
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10894
摘要： The present invention relates to a method of forming a self-aligned contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, an array area and a periphery area. The array area comprises a first gate electrode and a second gate electrode adjacent to the first gate electrode. The periphery area comprises at least a third gate electrode. A first doped area is formed over each of two opposite sides of each gate electrode. A first spacer is formed on a wall of each of the two opposite sides of the third gate electrode in the periphery area. Then, a second spacer is formed on a wall of each of the two opposite sides of the first and second gate electrodes in the array area. The first spacers are thicker than the second spacers, and the second spacers between the first and second gate electrodes are internal walls of a self-aligned contact hole between the first and second gate electrodes.
摘要翻译：本发明涉及在半导体晶片上形成自对准接触孔的方法。半导体晶片包括基板，阵列区域和周边区域。阵列区域包括与第一栅电极相邻的第一栅电极和第二栅电极。外围区域包括至少第三栅电极。在每个栅电极的两个相对侧的每一个上形成第一掺杂区。第一间隔件形成在周边区域中的第三栅电极的两个相对侧的每个的壁上。然后，在阵列区域中的第一和第二栅电极的两个相对侧的每一个的壁上形成第二间隔物。第一间隔物比第二间隔物厚，并且第一和第二栅电极之间的第二间隔物是第一和第二栅电极之间的自对准接触孔的内壁。

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