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1. 发明授权

US06787411B2 Method of manufacturing semiconductor memory device and semiconductor memory device 失效
标题翻译：制造半导体存储器件和半导体存储器件的方法
公开(公告)号：US06787411B2
公开(公告)日：2004-09-07
申请号：US10330448
申请日：2002-12-30
申请人： Teruaki Kisu , Kazuo Nakazato , Masahito Takahashi
发明人： Teruaki Kisu , Kazuo Nakazato , Masahito Takahashi
IPC分类号： H01L218244
CPC分类号： H01L27/108 , H01L27/0688 , H01L27/105 , H01L27/1052
摘要： Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
摘要翻译：公开了能够使存储单元尺寸小型化的增益单元结构及其制造方法。存储单元由读取MIS晶体管和写入MIS晶体管构成。读取MIS晶体管具有形成在半导体衬底的主表面上的一对n +型半导体区域（源极区域和漏极区域）和形成在n +型半导体区域13的路径上的第一栅极电极经由第一栅绝缘膜。写入MIS晶体管布置在读取MIS晶体管上，并且具有通过以此顺序层叠下半导体层（源极区），中间半导体层（沟道形成区）和上半导体层（漏极区）而形成的层叠结构。写入MIS晶体管具有垂直结构，其中第二栅极经由第二栅极绝缘膜布置在层状结构的两个侧壁上。

2. 发明授权

US06501116B2 Semiconductor memory device with MIS transistors 失效
标题翻译：具有MIS晶体管的半导体存储器件
公开(公告)号：US06501116B2
公开(公告)日：2002-12-31
申请号：US10026769
申请日：2001-12-27
申请人： Teruaki Kisu , Kazuo Nakazato , Masahito Takahashi
发明人： Teruaki Kisu , Kazuo Nakazato , Masahito Takahashi
IPC分类号： H01L2708
CPC分类号： H01L27/108 , H01L27/0688 , H01L27/105 , H01L27/1052
摘要： Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
摘要翻译：公开了能够使存储单元尺寸小型化的增益单元结构及其制造方法。存储单元由读取MIS晶体管和写入MIS晶体管构成。读取MIS晶体管具有形成在半导体衬底的主表面上的一对n +型半导体区域（源极区域和漏极区域）以及经由第一栅极绝缘膜形成在n +型半导体区域13的路径上的第一栅极电极。写入MIS晶体管布置在读取MIS晶体管上，并且具有通过以此顺序层叠下半导体层（源极区），中间半导体层（沟道形成区）和上半导体层（漏极区）而形成的层叠结构。写入MIS晶体管具有垂直结构，其中第二栅极经由第二栅极绝缘膜布置在层状结构的两个侧壁上。

3. 发明授权

US5598368A Batch erasable nonvolatile memory device and erasing method 失效
标题翻译：批量可擦除非易失性存储器件和擦除方法
公开(公告)号：US5598368A
公开(公告)日：1997-01-28
申请号：US445105
申请日：1995-05-19
申请人： Masahito Takahashi , Michiko Odagiri , Takeshi Furuno , Kazunori Furusawa , Masashi Wada
发明人： Masahito Takahashi , Michiko Odagiri , Takeshi Furuno , Kazunori Furusawa , Masashi Wada
IPC分类号： G11C17/00 , G11C16/02 , G11C16/16 , G11C16/34 , G11C13/00
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3409 , G11C16/3445 , G11C16/3468
摘要： A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.
摘要翻译：批量可擦除非易失性存储装置和使用该存储器单元的装置，该存储单元适于通过通过编程操作（包括预写操作）弹出在浮动栅极上累积的电荷来执行擦除操作，序列，用于读取擦除单元的存储单元并且在不存储电荷的浮动栅极上对那些非易失性存储单元执行预写操作的第一操作，用于在存储单元中执行批量擦除操作的第二操作在相对较大的擦除参考电压下具有相对大的能量的所述擦除单元的非易失性存储单元的高速度，用于执行所有擦除的非易失性存储单元的读操作的第三操作和对那些非易失性存储单元的写操作适于具有相对低的阈值电压，以及第四操作，用于以低速执行批量擦除操作所述擦除单元的非易失性存储单元在相对小的擦除参考电压下具有相对小的能量，或者设置有用于执行这些操作的自动擦除电路。

4. 发明授权

US06714447B2 Semiconductor device and a integrated circuit card 有权
标题翻译：半导体器件和集成电路卡
公开(公告)号：US06714447B2
公开(公告)日：2004-03-30
申请号：US10085037
申请日：2002-03-01
申请人： Akihiko Satoh , Masahito Takahashi
发明人： Akihiko Satoh , Masahito Takahashi
IPC分类号： G11C1604
CPC分类号： G11C16/3472 , G11C8/08 , G11C11/5628 , G11C16/0416 , G11C16/0483 , G11C16/08 , G11C16/3481
摘要： It is possible to suppress or prevent so-called write disturbance phenomenon from occurring in write-disabled non-selected memory cells in a semiconductor device, in any selected one of which data can be written electrically by means of the so-called tunneling phenomenon. In a flash memory that can disable writing of data by suppressing injection of electrons in the accumulation layer of each non-selected memory cell in which data is to be written with a writing disable voltage applied to the drain thereof before a write voltage is applied to the control gate electrode of each selected memory cell, the relationship among a writing disable voltage Vwd, a read voltage Vr applied to the drain of a selected memory cell from which data is to be read, and a punch-through withstand voltage BVds between the source and the drain of each selected memory cell is set to satisfy Vr
摘要翻译：可以抑制或防止在半导体器件中的写入禁止的非选择存储单元中发生所谓的写入干扰现象，在所选择的一个中，可以通过所谓的隧道现象将数据写入电。在闪速存储器中，通过在将写入电压施加到其上施加到其漏极的写入禁止电压之前，通过抑制要在其中写入数据的每个未选择存储器单元的累积层中的电子注入来禁止数据写入每个选择的存储单元的控制栅极电极，写入禁止电压Vwd，施加到要从其读取数据的所选择的存储单元的漏极的读取电压Vr与在其之间的穿透耐受电压BVds之间的关系每个选择的存储单元的源极和漏极被设置为满足Vr

5. 发明授权

US06646303B2 Nonvolatile semiconductor memory device and a method of manufacturing the same 有权
公开(公告)号：US06646303B2
公开(公告)日：2003-11-11
申请号：US09973022
申请日：2001-10-10
申请人： Akihiko Satoh , Masahito Takahashi , Takayuki Yoshitake
发明人： Akihiko Satoh , Masahito Takahashi , Takayuki Yoshitake
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： The present invention aims to provide high integration of a nonvolatile semiconductor memory device having lots of flash memory cells without causing a reduction in its operating speed. A width taken along a gate-width direction, of a lower conductor film for a floating gate electrode is made thinner than a minimum processing size F, and a width taken along the gate-width direction, of an upper conductor film for the floating gate electrode, which is provided with an insulating film disposed on source and drain regions interposed therebetween, is made thicker than the minimum processing size F, whereby a reduction in the ratio of coupling between a control gate electrode and a floating gate electrode due to the scaling down of a unit cell area is restrained.

6. 发明申请

US20060214254A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20060214254A1
公开(公告)日：2006-09-28
申请号：US11443226
申请日：2006-05-31
申请人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
发明人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , H01L21/28123 , H01L21/76224 , H01L21/823481 , H01L27/105 , H01L27/11546
摘要： To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
摘要翻译：为了抑制半导体衬底中的缺陷的发生，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

7. 发明申请

US20140191533A1 VEHICLE INTERIOR TRIM 审中-公开
标题翻译：汽车内饰
公开(公告)号：US20140191533A1
公开(公告)日：2014-07-10
申请号：US13806792
申请日：2011-06-20
申请人： Masahito Takahashi
发明人： Masahito Takahashi
IPC分类号： B60R13/02 , B60R21/04
CPC分类号： B60R13/02 , B60R13/025 , B60R21/04 , B60R2013/0287 , B60R2021/0407
摘要： Provided is a pillar trim (30) (a vehicle interior trim) with a main body part (32) formed in a hollow, three-dimensional structure by a thermoplastic synthetic resin. The exterior surface of the main body part (32) has a structure whereby an attachment surface (32a) attached to a vehicle structural member and a design surface (32b) inside the vehicle which are both joined together. In addition, the main body part (32) is formed of a bag-like construction that restricts the flow of internal air to the outside, and the main body part (32) distributes and absorbs impact forces from passenger during vehicle impact by using the internal pressure thereof.
摘要翻译：本发明提供一种具有通过热塑性合成树脂形成为中空三维结构的主体部分（32）的立柱装饰件（30）（车辆内饰件）。主体部（32）的外表面具有安装在车辆结构部件上的安装面（32a）和车辆内部的设计面（32b）两者结合的结构。此外，主体部32形成为限制内部空气向外部流动的袋状结构，主体部32通过使用本体部32在车辆撞击时分配和吸收乘客的冲击力，内部压力。

8. 发明授权

US07084477B2 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07084477B2
公开(公告)日：2006-08-01
申请号：US10600771
申请日：2003-06-23
申请人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
发明人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , H01L21/28123 , H01L21/76224 , H01L21/823481 , H01L27/105 , H01L27/11546
摘要： To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
摘要翻译：为了抑制在半导体衬底中发生的缺陷，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

9. 发明授权

US06420754B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06420754B2
公开(公告)日：2002-07-16
申请号：US09791832
申请日：2001-02-26
申请人： Masahito Takahashi , Shiro Akamatsu , Akihiko Satoh , Fukuo Owada , Masataka Kato
发明人： Masahito Takahashi , Shiro Akamatsu , Akihiko Satoh , Fukuo Owada , Masataka Kato
IPC分类号： H01L29792
CPC分类号： H01L27/11521 , G11C7/18 , G11C16/0416 , H01L27/115 , H01L29/42324
摘要： A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells. A hole for connecting the two layers of the gate electrode of a first field-effect transistor used as peripheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor, and the gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.
摘要翻译：用作外围电路的场效应晶体管的栅电极由与非易失性存储单元的双电平栅电极结构相同的栅电极结构构成。用于连接用作外围电路的第一场效应晶体管的栅电极的两层的孔设置在与栅电极的平面内的有源区二维重叠的位置处，并且用于连接两个用作外围电路的第二场效应晶体管的栅电极的层设置在与栅电极的平面内的隔离区域二维重叠的位置处。第一场效应晶体管的栅极长度比第二场效应晶体管的栅极长度长，第一场效应晶体管的栅极宽度比第二场效应晶体管的栅极宽。

10. 发明授权

US06423584B1 method for forming capacitors and field effect transistors in a semiconductor integrated circuit device 有权
公开(公告)号：US06423584B1
公开(公告)日：2002-07-23
申请号：US09811598
申请日：2001-03-20
申请人： Masahito Takahashi , Shiro Akamatsu , Akihiko Satoh , Fukuo Owada , Masataka Kato
发明人： Masahito Takahashi , Shiro Akamatsu , Akihiko Satoh , Fukuo Owada , Masataka Kato
IPC分类号： H01L2100
摘要： A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode. A hole for connecting between the two layers of the gate electrode of a first field-effect transistor used as perpheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting between the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor, and the gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.

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