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1. 发明申请

US20080270736A1 Information processing apparatus and access control method 有权
标题翻译：信息处理装置和访问控制方法
公开(公告)号：US20080270736A1
公开(公告)日：2008-10-30
申请号：US12075220
申请日：2008-03-10
申请人： Tsuyoshi Nishida , Gen Watanabe , Kazuyoshi Kuwahara , Hajime Sonobe
发明人： Tsuyoshi Nishida , Gen Watanabe , Kazuyoshi Kuwahara , Hajime Sonobe
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F9/30098 , G06F9/3824 , G06F9/3891
摘要： According to one embodiment, an information processing apparatus includes a processor including a register file which holds physical registers to which general purpose registers provided by an instruction set architecture are assigned, a virtual register assigning unit which assigns a virtual address in the main memory space to a physical register in the register file based on a request from a program, and records a correspondence between each of the virtual addresses and a corresponding one of the physical registers in a virtual register conversion table, and an access converting unit which determines whether or not a virtual address to be accessed is recorded in the virtual register conversion table managed by the virtual register assigning unit, and executes, when the virtual address is recorded therein, processing of accessing the physical register of which a correspondence to the virtual address is recorded in the virtual register conversion table.
摘要翻译：根据一个实施例，一种信息处理设备包括：处理器，包括：寄存器文件，其保存由指定集架构提供的通用寄存器被分配到的物理寄存器;虚拟寄存器分配单元，其将主存储器空间中的虚拟地址分配给基于来自程序的请求的寄存器文件中的物理寄存器，并且记录虚拟寄存器转换表中的每个虚拟地址和对应的一个物理寄存器之间的对应关系，以及访问转换单元，其确定是否要访问的虚拟地址被记录在由虚拟寄存器分配单元管理的虚拟寄存器转换表中，并且当虚拟地址被记录在其中时，执行访问与虚拟地址的对应关系的物理寄存器的处理被记录在虚拟寄存器转换表。

2. 发明申请

US20080267256A1 INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF PROCESSOR CIRCUIT 审中-公开
标题翻译：信号处理装置和处理器电路的控制方法
公开(公告)号：US20080267256A1
公开(公告)日：2008-10-30
申请号：US12110230
申请日：2008-04-25
申请人： Gen Watanabe , Tsuyoshi Nishida , Kazuyoshi Kuwahara , Hajime Sonobe
发明人： Gen Watanabe , Tsuyoshi Nishida , Kazuyoshi Kuwahara , Hajime Sonobe
IPC分类号： G01K13/00
CPC分类号： G01K7/425
摘要： According to one embodiment, an information processing apparatus comprises a plurality of temperature transmission sections provided in each of first and second semiconductor circuits, and configure to transmit first measured temperature of one of the first and second semiconductor circuits to the other of first and second semiconductor circuits when the first measured temperature is higher than a threshold temperature, and a plurality of operation speed varying sections provided in each of the first and second semiconductor circuits configure to reduce operation speed of the processor circuit possessed by the other of first and second semiconductor circuits, when the received first measured temperature is higher than the second measured temperature of the other of the first and second semiconductor circuits.
摘要翻译：根据一个实施例，信息处理设备包括设置在第一和第二半导体电路中的每一个中的多个温度传输部分，并且被配置为将第一和第二半导体电路之一的第一测量温度传输到第一和第二半导体中的另一个第一测量温度高于阈值温度的电路，并且设置在第一和第二半导体电路中的每一个中的多个操作速度变化部分被配置为降低由第一和第二半导体电路中的另一个拥有的处理器电路的操作速度当接收的第一测量温度高于第一和第二半导体电路中的另一个的第二测量温度时。

3. 发明申请

US20080270767A1 INFORMATION PROCESSING APPARATUS AND PROGRAM EXECUTION CONTROL METHOD 审中-公开
标题翻译：信息处理装置和程序执行控制方法
公开(公告)号：US20080270767A1
公开(公告)日：2008-10-30
申请号：US12099093
申请日：2008-04-07
申请人： Hajime Sonobe , Gen Watanabe , Tsuyoshi Nishida , Kazuyoshi Kuwahara
发明人： Hajime Sonobe , Gen Watanabe , Tsuyoshi Nishida , Kazuyoshi Kuwahara
IPC分类号： G06F9/44
CPC分类号： G06F1/3203 , G06F1/263 , G06F1/3293 , G06F9/30189 , G06F9/3877 , Y02D10/122
摘要： According to one embodiment, an information processing apparatus includes a first processor which has a first instruction set, a second processor which has a second instruction set, a storage unit which stores a program including a first program module which is described by using the second instruction set and causes the second processor to execute a first process including the arithmetic process, and a second program module which is described by using the first instruction set and causes the first processor to execute a process which is the same as the first process, and a control unit which switches a mode for executing the program between a first mode in which the first program module is assigned to the second processor and a second mode in which the second program module is assigned to the first processor.
摘要翻译：根据一个实施例，一种信息处理设备包括具有第一指令集的第一处理器，具有第二指令集的第二处理器，存储包括通过使用第二指令描述的第一程序模块的程序的存储单元设置并使第二处理器执行包括算术处理的第一处理，以及通过使用第一指令集描述的第二程序模块，并使第一处理器执行与第一处理相同的处理，控制单元，其将在第一模式被分配给第二处理器的第一模式和将第二程序模块分配给第一处理器的第二模式之间切换用于执行程序的模式。

4. 发明授权

US07971026B2 Information processing apparatus and access control method 有权
标题翻译：信息处理装置和访问控制方法
公开(公告)号：US07971026B2
公开(公告)日：2011-06-28
申请号：US12075220
申请日：2008-03-10
申请人： Tsuyoshi Nishida , Gen Watanabe , Kazuyoshi Kuwahara , Hajime Sonobe
发明人： Tsuyoshi Nishida , Gen Watanabe , Kazuyoshi Kuwahara , Hajime Sonobe
IPC分类号： G06F12/00
CPC分类号： G06F12/08 , G06F9/30098 , G06F9/3824 , G06F9/3891
摘要： According to one embodiment, an information processing apparatus includes a processor including a register file which holds physical registers to which general purpose registers provided by an instruction set architecture are assigned, a virtual register assigning unit which assigns a virtual address in the main memory space to a physical register in the register file based on a request from a program, and records a correspondence between each of the virtual addresses and a corresponding one of the physical registers in a virtual register conversion table, and an access converting unit which determines whether or not a virtual address to be accessed is recorded in the virtual register conversion table managed by the virtual register assigning unit, and executes, when the virtual address is recorded therein, processing of accessing the physical register of which a correspondence to the virtual address is recorded in the virtual register conversion table.
摘要翻译：根据一个实施例，一种信息处理设备包括：处理器，包括：寄存器文件，其保存由指定集架构提供的通用寄存器被分配到的物理寄存器;虚拟寄存器分配单元，其将主存储器空间中的虚拟地址分配给基于来自程序的请求的寄存器文件中的物理寄存器，并且记录虚拟寄存器转换表中的每个虚拟地址和对应的一个物理寄存器之间的对应关系，以及访问转换单元，其确定是否要访问的虚拟地址被记录在由虚拟寄存器分配单元管理的虚拟寄存器转换表中，并且当虚拟地址被记录在其中时，执行访问与虚拟地址的对应关系的物理寄存器的处理被记录在虚拟寄存器转换表。

5. 发明授权

US08108581B2 Information processing apparatus 有权
标题翻译：信息处理装置
公开(公告)号：US08108581B2
公开(公告)日：2012-01-31
申请号：US12816944
申请日：2010-06-16
申请人： Kazuyoshi Kuwahara , Isamu Uchiyama
发明人： Kazuyoshi Kuwahara , Isamu Uchiyama
IPC分类号： G06F13/26
CPC分类号： G06F13/385 , G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： According to one embodiment, an information processing apparatus including a suspension/resume function includes a bus controller which controls a bus capable of transmitting data at a first transmission speed or a second transmission speed lower than the first transmission speed, a storage module which stores setting information for limiting a data transmission speed of the bus to the second transmission speed, an initializing module which initializes the bus controller so as to limit the data transmission speed of the bus to the second transmission speed if the setting information is stored in the storage module when the apparatus is activated or returned from a suspended state, and a controller which stores the setting information into the storage module and makes the apparatus transit to the suspended state and return from the suspended state, when the transmission speed of the bus is limited to the second transmission speed.
摘要翻译：根据一个实施例，包括暂停/恢复功能的信息处理设备包括总线控制器，其控制能够以低于第一传输速度的第一传输速度或第二传输速度传输数据的总线;存储模块，其存储设置用于将总线的数据传输速度限制到第二传输速度的信息;初始化模块，其将总线控制器初始化，以便如果设置信息存储在存储模块中，则将总线的数据传输速度限制为第二传输速度当设备从暂停状态被激活或返回时，以及将设置信息存储到存储模块中并使设备转移到暂停状态并从暂停状态返回的控制器，当总线的传输速度被限制为第二传输速度。

6. 发明授权

US4460953A Signal voltage dividing circuit 失效
标题翻译：信号分压电路
公开(公告)号：US4460953A
公开(公告)日：1984-07-17
申请号：US375585
申请日：1982-05-06
申请人： Isao Fukushima , Kazuyoshi Kuwahara , Hideo Nishijima , Yasunori Kobori , Keiichi Itoigawa
发明人： Isao Fukushima , Kazuyoshi Kuwahara , Hideo Nishijima , Yasunori Kobori , Keiichi Itoigawa
IPC分类号： H03H19/00 , H02M3/06
CPC分类号： H03H19/004
摘要： A signal voltage dividing circuit in which two switched capacitors each including an input terminal, an output terminal and a capacitor connected selectively to the input terminal or the output terminal are connected in series and driven in opposite phase with each other. A holding capacitor is connected between the junction of the two switched capacitors and a reference potential. An input signal is supplied across the two switched capacitors to produce a divided output signal from the junction of the two switched capacitors.
摘要翻译：一种信号分压电路，其中包括输入端子，输出端子和选择性地连接到输入端子或输出端子的电容器的两个开关电容器串联连接并且彼此相反地驱动。保持电容器连接在两个开关电容器的结和参考电位之间。在两个开关电容器之间提供输入信号，以产生来自两个开关电容器的结的分压输出信号。

7. 发明授权

US07016395B2 Method and apparatus for performing wireless communication using spread spectrum-frequency hopping 有权
公开(公告)号：US07016395B2
公开(公告)日：2006-03-21
申请号：US10025489
申请日：2001-12-26
申请人： Jun Watanabe , Kazuyoshi Kuwahara
发明人： Jun Watanabe , Kazuyoshi Kuwahara
IPC分类号： H04B1/69
CPC分类号： H04B1/7143 , H04B1/715 , H04B2001/7154
摘要： A wireless communication apparatus conducts wireless communication of a spread spectrum communication system that performs frequency hopping using a plurality of frequency channels having different frequencies and defined in a usable frequency band. The apparatus includes a unit which detects a carrier of another wireless communication system that is predetermined, and a unit which excludes a frequency channel of the plurality of frequency channels in which the carrier of the wireless communication system is detected, from frequency channels targeted for the frequency hopping.

8. 发明授权

US5893812A Driving force distributing system for vehicle 失效
标题翻译：车辆驱动力分配系统
公开(公告)号：US5893812A
公开(公告)日：1999-04-13
申请号：US857562
申请日：1997-05-16
申请人： Katsuyuki Narai , Katsuhiro Kitamura , Kazuyoshi Kuwahara , Kenji Honda , Tetsushi Asano , Yasuji Shibahata , Kazuhiro Wada , Koji Yokomizo
发明人： Katsuyuki Narai , Katsuhiro Kitamura , Kazuyoshi Kuwahara , Kenji Honda , Tetsushi Asano , Yasuji Shibahata , Kazuhiro Wada , Koji Yokomizo
IPC分类号： B60K17/00 , B60K17/16 , B60K23/04 , F16H48/20
CPC分类号： B60K17/16 , B60K23/04 , B60K17/00
摘要： A driving force distributing device is provided for distributing a driving force of an engine to the left and right wheels of a vehicle by bringing a pair of hydraulic clutches into and out of their engaged states. The distributing device includes a hydraulic pump mounted within a casing thereof and driven through gears by a half shaft connected to one of the wheels. An oil passage interconnects the hydraulic pump and the hydraulic clutches, the oil passage being defined in a casing. A valve block is coupled to an upper surface of the casing. Thus, the oil passages interconnecting the hydraulic pump and the hydraulic clutches of the driving force distributing device can be compactly formed.
摘要翻译：驱动力分配装置用于通过使一对液压离合器进入和离开其接合状态来分配发动机的驱动力到车辆的左右轮。分配装置包括安装在其壳体内的液压泵，并通过连接到一个车轮的半轴通过齿轮驱动。油路将液压泵和液压离合器相互连接，油路限定在壳体中。阀块联接到壳体的上表面。因此，可以紧凑地形成将液压泵与驱动力分配装置的液压离合器相互连接的油路。

9. 发明授权

US3949161A Video signal reproducing system 失效
标题翻译：视频信号再生系统
公开(公告)号：US3949161A
公开(公告)日：1976-04-06
申请号：US490062
申请日：1974-07-19
申请人： Tooru Fujishima , Naoto Nishimura , Kazuyoshi Kuwahara , Shinji Ozaki , Masahiko Fujita
发明人： Tooru Fujishima , Naoto Nishimura , Kazuyoshi Kuwahara , Shinji Ozaki , Masahiko Fujita
IPC分类号： G11B7/00 , G11B7/003 , H04N3/38 , H04N5/84 , H04N9/11 , H04N5/36
CPC分类号： H04N3/38 , H04N5/843 , H04N9/11
摘要： A video signal reproducing system comprising means for driving a web of recording medium such as a tape at a constant speed, a self-scanned linear photoelectronic image device disposed for scanning in a direction perpendicular to the traveling direction of the recording medium, a clock pulse generator for applying clock pulses to this image device, and a light source for illuminating the recording medium, whereby information optically recorded on the recording medium can be scanned in a two-dimensional fashion to reproduce a video signal such as a television signal.
摘要翻译：一种视频信号再现系统，包括用于以恒定速度驱动诸如磁带的记录介质的卷筒纸的装置，设置用于沿与记录介质行进方向垂直的方向进行扫描的自扫描线性光电子图像装置，时钟脉冲用于向该图像装置施加时钟脉冲的发光器和用于照亮记录介质的光源，由此可以以二维方式扫描记录在记录介质上的信息，以再现诸如电视信号的视频信号。

10. 发明申请

US20100332708A1 Information Processing Apparatus 有权
标题翻译：信息处理装置
公开(公告)号：US20100332708A1
公开(公告)日：2010-12-30
申请号：US12816944
申请日：2010-06-16
申请人： Kazuyoshi Kuwahara , Isamu Uchiyama
发明人： Kazuyoshi Kuwahara , Isamu Uchiyama
IPC分类号： G06F13/36
CPC分类号： G06F13/385 , G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： According to one embodiment, an information processing apparatus including a suspension/resume function includes a bus controller which controls a bus capable of transmitting data at a first transmission speed or a second transmission speed lower than the first transmission speed, a storage module which stores setting information for limiting a data transmission speed of the bus to the second transmission speed, an initializing module which initializes the bus controller so as to limit the data transmission speed of the bus to the second transmission speed if the setting information is stored in the storage module when the apparatus is activated or returned from a suspended state, and a controller which stores the setting information into the storage module and makes the apparatus transit to the suspended state and return from the suspended state, when the transmission speed of the bus is limited to the second transmission speed.
摘要翻译：根据一个实施例，包括暂停/恢复功能的信息处理设备包括总线控制器，其控制能够以低于第一传输速度的第一传输速度或第二传输速度传输数据的总线;存储模块，其存储设置用于将总线的数据传输速度限制到第二传输速度的信息;初始化模块，其将总线控制器初始化，以便如果设置信息存储在存储模块中，则将总线的数据传输速度限制为第二传输速度当设备从暂停状态被激活或返回时，以及将设置信息存储到存储模块中并使设备转移到暂停状态并从暂停状态返回的控制器，当总线的传输速度被限制为第二传输速度。

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