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1. 发明授权

US07834701B2 Bias circuit and semiconductor integrated circuit including the bias circuit 有权
标题翻译：偏置电路和半导体集成电路包括偏置电路
公开(公告)号：US07834701B2
公开(公告)日：2010-11-16
申请号：US12519291
申请日：2008-05-28
申请人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
发明人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
IPC分类号： H03F3/04
CPC分类号： H03F3/45475 , H03F1/0261 , H03F1/34 , H03F3/3022 , H03F3/347 , H03F3/45928 , H03F3/68 , H03F2203/45136
摘要： A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.
摘要翻译：多个模拟信号通过各自的电容器C输入到模拟信号处理电路ANA2的输入端子。在偏置电路Bias中，用于向模拟信号处理电路ANA2提供诸如模拟信号的信号地的偏置电压，运算放大器OpAS，偏置电压VIr从内置差分放大器电路的非反相输入VIP输入，内置输出放大器电路OA1的输出端连接到差分放大器的反相输入端VIM 放大电路DA，从而获得电压跟随器。此外，设置多个输出放大器电路OA2至OAn，使得其输入端连接到差分放大器电路DA的输出端，并且输出端连接到模拟信号处理电路ANA2的输入端IN1至INn。

2. 发明申请

US20100045382A1 BIAS CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE BIAS CIRCUIT 有权
标题翻译：偏置电路和半导体集成电路，包括偏置电路
公开(公告)号：US20100045382A1
公开(公告)日：2010-02-25
申请号：US12519291
申请日：2008-05-28
申请人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
发明人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
IPC分类号： H03F3/34
CPC分类号： H03F3/45475 , H03F1/0261 , H03F1/34 , H03F3/3022 , H03F3/347 , H03F3/45928 , H03F3/68 , H03F2203/45136
摘要： A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.
摘要翻译：多个模拟信号通过各自的电容器C输入到模拟信号处理电路ANA2的输入端子。在偏置电路Bias中，用于向模拟信号处理电路ANA2提供诸如模拟信号的信号地的偏置电压，运算放大器OpAS，偏置电压VIr从内置差分放大器电路的非反相输入VIP输入，内置输出放大器电路OA1的输出端连接到差分放大器的反相输入端VIM 放大电路DA，从而获得电压跟随器。此外，设置多个输出放大器电路OA2至OAn，使得其输入端连接到差分放大器电路DA的输出端，并且输出端连接到模拟信号处理电路ANA2的输入端IN1至INn。

3. 发明申请

US20060132225A1 Standard voltage generation circuit 审中-公开
标题翻译：标准电压发生电路
公开(公告)号：US20060132225A1
公开(公告)日：2006-06-22
申请号：US11317173
申请日：2005-12-27
申请人： Junichi Naka , Michiko Tokumaru , Yoichi Okamoto , Koji Oka
发明人： Junichi Naka , Michiko Tokumaru , Yoichi Okamoto , Koji Oka
IPC分类号： G05F1/10
CPC分类号： G05F3/262 , G05F3/242
摘要： A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.
摘要翻译：标准电压产生电路具有当标准电压达到稳定电压点时自动停止充电的功能，通过在从待机状态转换到正常工作状态的过程中快速充电标准稳压电容器。标准电压产生电路还具有通过在从待机状态转换到正常工作状态期间电容器的分压效应将电路的输出端子预充电到接近稳定电压的功能。因此，当包括在标准电压发生电路中的模拟电路的状态从其断开状态变为其接通状态时，可以防止在标准电压达到稳定电压之前所需的时间量的增加。

4. 发明申请

US20100109763A1 STANDARD VOLTAGE GENERATION CIRCUIT 审中-公开
标题翻译：标准电压发生电路
公开(公告)号：US20100109763A1
公开(公告)日：2010-05-06
申请号：US12686494
申请日：2010-01-13
申请人： Junichi Naka , Michiko Tokumaru , Yoichi Okamoto , Koji Oka
发明人： Junichi Naka , Michiko Tokumaru , Yoichi Okamoto , Koji Oka
IPC分类号： G05F1/10
CPC分类号： G05F3/262 , G05F3/242
摘要： A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.
摘要翻译：标准电压产生电路具有当标准电压达到稳定电压点时自动停止充电的功能，通过在从待机状态转换到正常工作状态的过程中快速充电标准稳压电容器。标准电压产生电路还具有通过在从待机状态转换到正常工作状态期间电容器的分压效应将电路的输出端子预充电到接近稳定电压的功能。因此，当包括在标准电压发生电路中的模拟电路的状态从其断开状态变为其接通状态时，可以防止在标准电压达到稳定电压之前所需的时间量的增加。

5. 发明申请

US20070006110A1 Net list conversion method, net list conversion device, still-state leak current detection method, and still-state leak current detection device 审中-公开
标题翻译：网络列表转换方法，网络列表转换装置，静态泄漏电流检测方法和静态泄漏电流检测装置
公开(公告)号：US20070006110A1
公开(公告)日：2007-01-04
申请号：US10574498
申请日：2004-05-17
申请人： Junichi Naka , Koji Oka
发明人： Junichi Naka , Koji Oka
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： As shown in FIG. 1, a gate terminal of a MOS transistor or an input terminal of a logic gate, which are included in a through current detection target net list, are extracted, and a resistor is inserted between the gate terminal of the MOS transistor or the input terminal of the logic gate and a power supply, and between the gate terminal of the MOS transistor or the input terminal of the logic gate and a reference voltage, respectively, thereby to perform net list conversion, and thereafter, DC analysis is executed. Therefore, a MOS transistor in which through current might occur can be detected, leading to reliable detection of through current that cannot be easily detected by the conventional DC analysis simulation, and reliable detection of a transistor in which through current might occur, in the through current detection target circuit.
摘要翻译：如图所示。如图1所示，提取包括在通过电流检测对象网表中的MOS晶体管的栅极端子或逻辑门的输入端子，并且在MOS晶体管的栅极端子或输入端子之间插入电阻器逻辑门和电源之间，以及MOS晶体管的栅极端子或逻辑门的输入端子和参考电压之间，从而进行网络列表转换，之后执行DC分析。因此，可以检测到可能发生通过电流的MOS晶体管，导致对通过常规DC分析模拟不能容易地检测到的通过电流的可靠检测，以及在通孔中可能发生通过电流的晶体管的可靠检测电流检测目标电路。

6. 发明授权

US06734817B2 A/D converter, method of A/D conversion, and signal processing device 失效
标题翻译： A / D转换器，A / D转换方法和信号处理装置
公开(公告)号：US06734817B2
公开(公告)日：2004-05-11
申请号：US10328159
申请日：2002-12-26
申请人： Junichi Naka , Yoshitsugu Inagaki , Hiroshi Sakura , Heiji Ikoma , Koji Oka , Youichi Okamoto , Daisuke Nomasaki
发明人： Junichi Naka , Yoshitsugu Inagaki , Hiroshi Sakura , Heiji Ikoma , Koji Oka , Youichi Okamoto , Daisuke Nomasaki
IPC分类号： H03M112
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12
摘要： When the performance of an A/D converter required by a system changes, power consumption of the overall system can be reduced. The resolution of an A/D converter is made variable by changing a current flowing through an amplifier by an external control signal that specifies the resolution. Thus, when the performance required by a system changes, it is possible to change the performance of the A/D converter and to prevent a performance overhead of the A/D converter. Consequently, power consumption of the A/D converter is reduced, and power consumption of the system as a whole is also reduced.
摘要翻译：当系统所需的A / D转换器的性能改变时，可以降低整个系统的功耗。通过用指定分辨率的外部控制信号改变流过放大器的电流，可以使A / D转换器的分辨率可变。因此，当系统所需的性能改变时，可以改变A / D转换器的性能并且防止A / D转换器的性能开销。因此，A / D转换器的功耗降低，整个系统的功耗也降低。

7. 发明授权

US06700524B2 A/D converter for performing pipeline processing 失效
标题翻译：用于执行流水线处理的A / D转换器
公开(公告)号：US06700524B2
公开(公告)日：2004-03-02
申请号：US10256238
申请日：2002-09-27
申请人： Junichi Naka , Yoichi Okamoto , Yoshitsugu Inagaki , Kenji Murata , Koji Oka
发明人： Junichi Naka , Yoichi Okamoto , Yoshitsugu Inagaki , Kenji Murata , Koji Oka
IPC分类号： H03M138
CPC分类号： H03M1/007 , H03M1/0695 , H03M1/44
摘要： An A/D converter comprises a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage performing a pipeline operation on an inputted analog voltage to output a digital voltage; a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal. Therefore, when resolution of the A/D converter, which is requested by the system, is changed, only the pipeline stages required for realizing the requested resolution are operated while the other pipeline stages are halted, whereby a reduction in power consumption of the A/D converter is realized and, simultaneously, a breakdown of an output from the A/D converter is avoided.
摘要翻译： A / D转换器包括一个其中多个流水线级串联连接的流水线阵列，每个流水线级对所输入的模拟电压进行流水线操作以输出数字电压; 根据指示分辨率的位数控制信号，输出指示每个流水线级的操作是否应被执行或停止的位数选择信号的位数控制电路; 以及根据位数控制信号补偿要输出的数字值的校正电路。因此，当系统请求的A / D转换器的分辨率改变时，仅在实现所请求的分辨率所需的流水线阶段在其它流水线级停止的同时被操作，从而降低了A / D转换器，同时避免了A / D转换器的输出故障。

8. 发明申请

US20120044103A1 PARALLEL INTERPOLATION A/D CONVERTER AND DIGITAL EQUALIZER 审中-公开
标题翻译：并行插值A / D转换器和数字均衡器
公开(公告)号：US20120044103A1
公开(公告)日：2012-02-23
申请号：US13287617
申请日：2011-11-02
申请人： Rie Kaihara , Masakazu Shigemori , Youichi Ogura , Junichi Naka , Tsuyoshi Matsushita
发明人： Rie Kaihara , Masakazu Shigemori , Youichi Ogura , Junichi Naka , Tsuyoshi Matsushita
IPC分类号： H03M1/36
CPC分类号： H03M1/204 , H03M1/365
摘要： A parallel interpolation A/D converter includes a reference voltage generation circuit configured to generate (m+1) different reference voltages VR1-VRm+1, where m is a positive integer, and VR1
摘要翻译：并行内插A / D转换器包括：参考电压产生电路，被配置为产生（m + 1）不同的参考电压VR1-VRm + 1，其中m是正整数，VR1

9. 发明授权

US4653963A Transport apparatus for flat articles 失效
标题翻译：扁平物品运输设备
公开(公告)号：US4653963A
公开(公告)日：1987-03-31
申请号：US823221
申请日：1986-01-28
申请人： Kozo Taneda , Masae Chiba , Junichi Naka , Shunichi Watanabe
发明人： Kozo Taneda , Masae Chiba , Junichi Naka , Shunichi Watanabe
IPC分类号： B65G51/26 , B65G51/04
CPC分类号： B65G51/26
摘要： In a transport apparatus, a plurality of flat bodies are respectively aligned uprightly and juxtaposed laterally to form a block of the flat bodies, the block is loaded in a movable capsule, and the capsule is transported under the application of air flow through a transport pipeline. A loading mechanism having a pair of openable and closable holding arms is disposed to oppose a loading opening of a loading station, and an unloading mechanism having a pair of openable and closable holding arms is disposed to oppose an unloading opening of an unloading station.
摘要翻译：在运送装置中，多个扁平体分别垂直并排并排并排成平行体的块体，该块被装载在可移动的胶囊中，并且胶囊在空气流的运送下通过运输管线。具有一对可打开和关闭的保持臂的装载机构设置成与装载站的装载开口相对，并且具有一对可打开和关闭的保持臂的卸载机构设置成与卸载站的卸载开口相对。

10. 发明授权

US07642944B2 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：US07642944B2
公开(公告)日：2010-01-05
申请号：US11919235
申请日：2007-03-19
申请人： Junichi Naka
发明人： Junichi Naka
IPC分类号： H03M1/36
CPC分类号： H03M1/129 , H03M1/365
摘要： A full-flash A/D converter, including a differential amplifier circuit row and a voltage comparison circuit row, has an adjusting circuit 107 for making the output dynamic range of differential amplifier circuits accurately fall within the input dynamic range of voltage comparison circuits. The adjusting circuit 107 includes a reference voltage generation circuit 119, which has therein voltage generation circuits 122 whose resistors are connected in series. By this series connection, the area of the voltage generation circuits 122 is reduced, while the output dynamic range of the differential amplifier circuits A1 to Am+1 in the differential amplifier circuit row 102 accurately falls within the input dynamic range of the voltage comparison circuits Cr1 to Crm+1 in the voltage comparison circuit row 103. Furthermore, half-circuits in the voltage generation circuits 122 are used to generate reference voltages, whereby the area of the voltage generation circuits is reduced further.
摘要翻译：包括差分放大器电路行和电压比较电路行的全闪存A / D转换器具有用于使差分放大器电路的输出动态范围准确地落入电压比较电路的输入动态范围内的调整电路107。调整电路107包括参考电压产生电路119，其具有其电阻器串联连接的电压产生电路122。通过该串联连接，电压发生电路122的面积减小，差分放大电路列102的差分放大电路A1〜Am + 1的输出动态范围正确地落入电压比较电路的输入动态范围 Cr1〜Crm + 1。此外，电压产生电路122中的半电路用于产生参考电压，从而进一步降低电压产生电路的面积。

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