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    • 1. 发明授权
    • Vehicle door frame structure
    • 车门框架结构
    • US08458959B2
    • 2013-06-11
    • US12593645
    • 2008-03-28
    • Yasuhiro OhtakeKenji MurataShigenobu OhsawaJiro Yoshihara
    • Yasuhiro OhtakeKenji MurataShigenobu OhsawaJiro Yoshihara
    • B60J5/04
    • B60J5/0402B60J10/21B60J10/86B60J10/88
    • A vehicle door frame structure has an upper sash member located along a roof panel of a vehicle body and also has a vertical pillar sash member located along a center pillar of the vehicle body. The upper sash member has, at its linear end joined to the vertical pillar sash member side, an aesthetically designed section and an inner frame portion. The aesthetically designed section is located on the outer side of the door, and the inner frame portion is located closer to the vehicle interior than the aesthetically designed section and is shorter in length than the aesthetically designed section. The vertical pillar sash member has at its upper end a superposed contact section that is superposed, in the direction of the thickness of the door, on an end of the inner frame portion of the upper sash member, and the superposed contact section and the inner frame portion are joined together while being superposed on each other.
    • 车门框架结构具有沿着车身的车顶板定位的上框架构件,并且还具有沿着车身的中心柱定位的立柱框架构件。 上框架构件在其直线端部处连接到垂直支撑框架构件侧,具有美观设计的部分和内框架部分。 美观设计的部分位于门的外侧,并且内框架部分位于比美观设计的部分更靠近车辆内部并且比美观设计的部分的长度更短。 立柱框架构件的上端具有重叠的接触部分,其在门的厚度方向上重叠在上框架构件的内框架部分的端部上,并且叠置的接触部分和内部 框架部分彼此叠合在一起。
    • 3. 发明申请
    • CLOCK AND DATA RECOVERY CIRCUIT
    • 时钟和数据恢复电路
    • US20120105115A1
    • 2012-05-03
    • US13344201
    • 2012-01-05
    • Michiyo YAMAMOTOKenji MurataKazuya Hatooka
    • Michiyo YAMAMOTOKenji MurataKazuya Hatooka
    • H03L7/06
    • H04L7/0337H03L7/091H03L7/0996
    • A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.
    • 时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路,采样电路,对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样,并产生多个 数据信号,数据恢复单元,其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元,存储选择信号。 数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。
    • 6. 发明授权
    • Semiconductor integrated circuit, D-A converter device, and A-D converter device
    • 半导体集成电路,D-A转换器和A-D转换器
    • US06777775B2
    • 2004-08-17
    • US10187378
    • 2002-07-02
    • Yoshinori MiyadaKenji MurataDaisuke Nomasaki
    • Yoshinori MiyadaKenji MurataDaisuke Nomasaki
    • H01L2900
    • H01L27/0805H01L23/5225H01L2924/0002H01L2924/00
    • A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.
    • 半导体集成电路具有多个电容器单元,并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时,屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此,利用该屏蔽布线,可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。
    • 7. 发明授权
    • A/D conversion method for serial/parallel A/D converter, and serial/parallel A/D converter
    • 串行/并行A / D转换器和串行/并行A / D转换器的A / D转换方法
    • US06741192B2
    • 2004-05-25
    • US10615391
    • 2003-07-09
    • Kenji MurataDaisuke Nomasaki
    • Kenji MurataDaisuke Nomasaki
    • H03M900
    • H03M1/148H03M1/362
    • The present invention provides a serial/parallel A/D converter which is capable of performing a high-speed and high-accuracy operation even in the case where an analog input voltage Vin greatly varies in a period between a previous sampling period in which the analog input voltage is held and the next sampling period, when converting the analog input voltage Vin input into a digital value. This serial/parallel A/D converter includes a lower-order reference voltage initializing circuit 8 for initializing a lower-order reference voltage to an initialization voltage Vrc 23. The initialization voltage Vrc 23 is generated as the lower-order reference voltage in an arbitrary period from the start of sampling of the analog input voltage until the start of a comparison operation for the lower-order reference voltage, the value of the lower-order reference voltage is changed from the value of the initialization voltage to a voltage value which is decided on the basis of higher-order code selection signals P0C-P3C from a higher-order code selecting circuit 14, and the value of the lower-order reference voltage which is decided on the basis of the higher-order code selection signals P0C-P3C is compared with the value of the analog input voltage.
    • 本发明提供一种串行/并行A / D转换器,其即使在模拟输入电压Vin在先前的采样周期之间的时段内大大变化的情况下也能够执行高速和高精度的操作,其中模拟 当将模拟输入电压Vin输入转换为数字值时,保持输入电压和下一个采样周期。 该串/并行A / D转换器包括用于将低阶参考电压初始化为初始化电压Vrc 23的低阶参考电压初始化电路8.初始化电压Vrc 23作为任意的低阶参考电压生成 从开始对模拟输入电压的采样开始到低阶参考电压的比较操作开始之间的时间段,将低阶参考电压的值从初始化电压的值改变为电压值,即, 基于来自高阶代码选择电路14的高阶代码选择信号P0C-P3C和基于较高阶代码选择信号P0C-P3C决定的低阶参考电压的值, P3C与模拟输入电压的值进行比较。
    • 9. 发明授权
    • Non-directional speaker system with point sound source
    • 带点声源的无方位扬声器系统
    • US5812685A
    • 1998-09-22
    • US610999
    • 1996-03-07
    • Takeshi FujitaKenji Murata
    • Takeshi FujitaKenji Murata
    • H04R1/26G10K15/00H04R1/40H04S1/00H04R1/02
    • H04R1/403
    • A speaker system is disclosed which is capable of supplying reproduced sounds vibrating in substantially the same manner as in the respiratory sphere to human's sense of hearing by using conventional unidirectional speaker units in combination in a contrived arrangement, and by applying real time digital signal processing by means of a digital signal processor to the speaker units to cancel a peak and a dip in frequency response and in phase response through inverse correction which cannot be canceled only by improving the arrangement of the speaker units, thereby forming a sound emitter capable of providing ideal reproduced sounds. The speaker system comprises an enclosure EC having a basic structure of a hollow 32-hedron composed of 12 pentagonal flat surfaces 1 and 20 hexagonal flat surfaces 2, speaker units 7, 8 or 78 mounted in all or 25-31 of the 32 surfaces, and a real time digital signal processing system inserted in a input line of each of the speaker units 7, 8 or 78. The digital signal processing system inverse-characteristically filtering driving signals of the speaker units to evenly correcting a peak 4 and a dip 5 caused in frequency response and in phase response of each of the speaker units 7, 8 or 78.
    • 公开了一种扬声器系统,其能够通过以设计的方式组合使用常规的单向扬声器单元,并且通过应用实时数字信号处理来提供以与呼吸球基本相同的方式振动的再现声音,以使人的听觉感受 扬声器单元的数字信号处理器的装置,用于消除频率响应中的峰值和下降以及通过反向校正的相位响应,这不能仅通过改善扬声器单元的布置来消除,从而形成能够提供理想的声发射器 再现的声音。 扬声器系统包括具有由12个五边形平面1和20六角形平面2,扬声器单元7,8或78组成的中空32角的基本结构的外壳EC,其安装在32个表面的全部或25-31中, 以及插入每个扬声器单元7,8或78的输入线中的实时数字信号处理系统。数字信号处理系统对扬声器单元的驱动信号进行逆特性滤波以均匀地校正峰值4和倾角5 在每个扬声器单元7,8或78的频率响应和相位响应中引起。