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1. 发明申请

US20120044103A1 PARALLEL INTERPOLATION A/D CONVERTER AND DIGITAL EQUALIZER 审中-公开
标题翻译：并行插值A / D转换器和数字均衡器
公开(公告)号：US20120044103A1
公开(公告)日：2012-02-23
申请号：US13287617
申请日：2011-11-02
申请人： Rie Kaihara , Masakazu Shigemori , Youichi Ogura , Junichi Naka , Tsuyoshi Matsushita
发明人： Rie Kaihara , Masakazu Shigemori , Youichi Ogura , Junichi Naka , Tsuyoshi Matsushita
IPC分类号： H03M1/36
CPC分类号： H03M1/204 , H03M1/365
摘要： A parallel interpolation A/D converter includes a reference voltage generation circuit configured to generate (m+1) different reference voltages VR1-VRm+1, where m is a positive integer, and VR1
摘要翻译：并行内插A / D转换器包括：参考电压产生电路，被配置为产生（m + 1）不同的参考电压VR1-VRm + 1，其中m是正整数，VR1

2. 发明授权

US08487802B2 Comparator and analog-to-digital converter 有权
标题翻译：比较器和模数转换器
公开(公告)号：US08487802B2
公开(公告)日：2013-07-16
申请号：US13052817
申请日：2011-03-21
申请人： Junichi Naka , Masakazu Shigemori
发明人： Junichi Naka , Masakazu Shigemori
IPC分类号： H03M1/34
CPC分类号： H03K5/249
摘要： Increase of power consumption is reduced, and the operational speed is improved. A comparator includes a comparing section which outputs a result of comparison between a first voltage and a second voltage which constitute an input differential signal, a first positive feedback section which operates in synchronism with a first clock signal, amplifies the result from the comparing section, and outputs the amplified result to an output node pair, and a second positive feedback section which operates in synchronism with a second clock signal, and provides positive feedback to the output node pair.
摘要翻译：降低功耗增加，运行速度提高。比较器包括比较部分，其输出构成输入差分信号的第一电压和第二电压之间的比较结果，与第一时钟信号同步操作的第一正反馈部分，放大比较部分的结果，并将放大的结果输出到输出节点对，以及与第二时钟信号同步工作的第二正反馈部分，并向输出节点对提供正反馈。

3. 发明授权

US07834701B2 Bias circuit and semiconductor integrated circuit including the bias circuit 有权
标题翻译：偏置电路和半导体集成电路包括偏置电路
公开(公告)号：US07834701B2
公开(公告)日：2010-11-16
申请号：US12519291
申请日：2008-05-28
申请人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
发明人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
IPC分类号： H03F3/04
CPC分类号： H03F3/45475 , H03F1/0261 , H03F1/34 , H03F3/3022 , H03F3/347 , H03F3/45928 , H03F3/68 , H03F2203/45136
摘要： A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.
摘要翻译：多个模拟信号通过各自的电容器C输入到模拟信号处理电路ANA2的输入端子。在偏置电路Bias中，用于向模拟信号处理电路ANA2提供诸如模拟信号的信号地的偏置电压，运算放大器OpAS，偏置电压VIr从内置差分放大器电路的非反相输入VIP输入，内置输出放大器电路OA1的输出端连接到差分放大器的反相输入端VIM 放大电路DA，从而获得电压跟随器。此外，设置多个输出放大器电路OA2至OAn，使得其输入端连接到差分放大器电路DA的输出端，并且输出端连接到模拟信号处理电路ANA2的输入端IN1至INn。

4. 发明申请

US20100045382A1 BIAS CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE BIAS CIRCUIT 有权
标题翻译：偏置电路和半导体集成电路，包括偏置电路
公开(公告)号：US20100045382A1
公开(公告)日：2010-02-25
申请号：US12519291
申请日：2008-05-28
申请人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
发明人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
IPC分类号： H03F3/34
CPC分类号： H03F3/45475 , H03F1/0261 , H03F1/34 , H03F3/3022 , H03F3/347 , H03F3/45928 , H03F3/68 , H03F2203/45136
摘要： A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.
摘要翻译：多个模拟信号通过各自的电容器C输入到模拟信号处理电路ANA2的输入端子。在偏置电路Bias中，用于向模拟信号处理电路ANA2提供诸如模拟信号的信号地的偏置电压，运算放大器OpAS，偏置电压VIr从内置差分放大器电路的非反相输入VIP输入，内置输出放大器电路OA1的输出端连接到差分放大器的反相输入端VIM 放大电路DA，从而获得电压跟随器。此外，设置多个输出放大器电路OA2至OAn，使得其输入端连接到差分放大器电路DA的输出端，并且输出端连接到模拟信号处理电路ANA2的输入端IN1至INn。

5. 发明申请

US20060132225A1 Standard voltage generation circuit 审中-公开
标题翻译：标准电压发生电路
公开(公告)号：US20060132225A1
公开(公告)日：2006-06-22
申请号：US11317173
申请日：2005-12-27
申请人： Junichi Naka , Michiko Tokumaru , Yoichi Okamoto , Koji Oka
发明人： Junichi Naka , Michiko Tokumaru , Yoichi Okamoto , Koji Oka
IPC分类号： G05F1/10
CPC分类号： G05F3/262 , G05F3/242
摘要： A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.
摘要翻译：标准电压产生电路具有当标准电压达到稳定电压点时自动停止充电的功能，通过在从待机状态转换到正常工作状态的过程中快速充电标准稳压电容器。标准电压产生电路还具有通过在从待机状态转换到正常工作状态期间电容器的分压效应将电路的输出端子预充电到接近稳定电压的功能。因此，当包括在标准电压发生电路中的模拟电路的状态从其断开状态变为其接通状态时，可以防止在标准电压达到稳定电压之前所需的时间量的增加。

6. 发明授权

US4653963A Transport apparatus for flat articles 失效
标题翻译：扁平物品运输设备
公开(公告)号：US4653963A
公开(公告)日：1987-03-31
申请号：US823221
申请日：1986-01-28
申请人： Kozo Taneda , Masae Chiba , Junichi Naka , Shunichi Watanabe
发明人： Kozo Taneda , Masae Chiba , Junichi Naka , Shunichi Watanabe
IPC分类号： B65G51/26 , B65G51/04
CPC分类号： B65G51/26
摘要： In a transport apparatus, a plurality of flat bodies are respectively aligned uprightly and juxtaposed laterally to form a block of the flat bodies, the block is loaded in a movable capsule, and the capsule is transported under the application of air flow through a transport pipeline. A loading mechanism having a pair of openable and closable holding arms is disposed to oppose a loading opening of a loading station, and an unloading mechanism having a pair of openable and closable holding arms is disposed to oppose an unloading opening of an unloading station.
摘要翻译：在运送装置中，多个扁平体分别垂直并排并排并排成平行体的块体，该块被装载在可移动的胶囊中，并且胶囊在空气流的运送下通过运输管线。具有一对可打开和关闭的保持臂的装载机构设置成与装载站的装载开口相对，并且具有一对可打开和关闭的保持臂的卸载机构设置成与卸载站的卸载开口相对。

7. 发明授权

US07642944B2 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：US07642944B2
公开(公告)日：2010-01-05
申请号：US11919235
申请日：2007-03-19
申请人： Junichi Naka
发明人： Junichi Naka
IPC分类号： H03M1/36
CPC分类号： H03M1/129 , H03M1/365
摘要： A full-flash A/D converter, including a differential amplifier circuit row and a voltage comparison circuit row, has an adjusting circuit 107 for making the output dynamic range of differential amplifier circuits accurately fall within the input dynamic range of voltage comparison circuits. The adjusting circuit 107 includes a reference voltage generation circuit 119, which has therein voltage generation circuits 122 whose resistors are connected in series. By this series connection, the area of the voltage generation circuits 122 is reduced, while the output dynamic range of the differential amplifier circuits A1 to Am+1 in the differential amplifier circuit row 102 accurately falls within the input dynamic range of the voltage comparison circuits Cr1 to Crm+1 in the voltage comparison circuit row 103. Furthermore, half-circuits in the voltage generation circuits 122 are used to generate reference voltages, whereby the area of the voltage generation circuits is reduced further.
摘要翻译：包括差分放大器电路行和电压比较电路行的全闪存A / D转换器具有用于使差分放大器电路的输出动态范围准确地落入电压比较电路的输入动态范围内的调整电路107。调整电路107包括参考电压产生电路119，其具有其电阻器串联连接的电压产生电路122。通过该串联连接，电压发生电路122的面积减小，差分放大电路列102的差分放大电路A1〜Am + 1的输出动态范围正确地落入电压比较电路的输入动态范围 Cr1〜Crm + 1。此外，电压产生电路122中的半电路用于产生参考电压，从而进一步降低电压产生电路的面积。

8. 发明申请

US20090179787A1 COMPARATOR AND A/D CONVERTER 有权
标题翻译：比较器和A / D转换器
公开(公告)号：US20090179787A1
公开(公告)日：2009-07-16
申请号：US12093565
申请日：2006-04-18
申请人： Junichi Naka , Koji Sushihara
发明人： Junichi Naka , Koji Sushihara
IPC分类号： H03M1/12 , H03K5/22
CPC分类号： H03M1/0607 , H03K5/2481 , H03M1/204 , H03M1/362
摘要： A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.
摘要翻译：一种用于并行型A / D转换器的比较器，其中比较器100包括复位晶体管mra和mrb。当比较器100处于复位状态时，将时钟信号的反相信号/ CLK提供给PMOS复位晶体管mra和mrb，以便将两个作为差分对的内部节点Va和Vb的两个电压强制复位到复位晶体管mra和mrb的预定复位电压。以预定的延迟产生时钟信号的反相信号/ CLK。因此，当比较器100处于复位状态时，消除内部节点Va和Vb的复位的时间点比比较器执行比较操作的时间延迟。因此，即使时钟信号的频率和模拟输入信号的频率高，形成差分对的内部节点的电压在比较器处于复位状态时也是平衡的，从而提高电压比较精度。

9. 发明授权

US4583884A Transport apparatus for flat articles 失效
公开(公告)号：US4583884A
公开(公告)日：1986-04-22
申请号：US619871
申请日：1984-06-12
申请人： Kozo Taneda , Masae Chiba , Junichi Naka , Shunichi Watanabe
发明人： Kozo Taneda , Masae Chiba , Junichi Naka , Shunichi Watanabe
IPC分类号： B65G51/26
CPC分类号： B65G51/26
摘要： In a transport apparatus, a plurality of flat bodies are respectively aligned uprightly and juxtaposed laterally to form a block of the flat bodies, the block is loaded in a movable capsule, and the capsule is transported under the application of air flow through a transport pipeline. A loading mechanism having a pair of openable and closable holding arms is disposed to oppose a loading opening of a loading station, and an unloading mechanism having a pair of openable and closable holding arms is disposed to oppose an unloading opening of an unloading station.

10. 发明申请

US20100109763A1 STANDARD VOLTAGE GENERATION CIRCUIT 审中-公开
标题翻译：标准电压发生电路
公开(公告)号：US20100109763A1
公开(公告)日：2010-05-06
申请号：US12686494
申请日：2010-01-13
申请人： Junichi Naka , Michiko Tokumaru , Yoichi Okamoto , Koji Oka
发明人： Junichi Naka , Michiko Tokumaru , Yoichi Okamoto , Koji Oka
IPC分类号： G05F1/10
CPC分类号： G05F3/262 , G05F3/242
摘要： A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.
摘要翻译：标准电压产生电路具有当标准电压达到稳定电压点时自动停止充电的功能，通过在从待机状态转换到正常工作状态的过程中快速充电标准稳压电容器。标准电压产生电路还具有通过在从待机状态转换到正常工作状态期间电容器的分压效应将电路的输出端子预充电到接近稳定电压的功能。因此，当包括在标准电压发生电路中的模拟电路的状态从其断开状态变为其接通状态时，可以防止在标准电压达到稳定电压之前所需的时间量的增加。

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