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1. 发明申请

WO2002078197A2 SAMPLING METHOD, RECONSTRUCTION METHOD, AND DEVICE FOR SAMPLING AND/OR RECONSTRUCTING SIGNALS 审中-公开
标题翻译：采样方法，重建方法和用于采样和/或重建信号的设备
公开(公告)号：WO2002078197A2
公开(公告)日：2002-10-03
申请号：PCT/EP2002/003380
申请日：2002-03-26
申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , VETTERLI, Martin , MARZILIANO, Pina , BLU, Thierry
发明人： VETTERLI, Martin , MARZILIANO, Pina , BLU, Thierry
IPC分类号： H03M112
CPC分类号： H04B1/707 , H03M1/1285 , H03M1/66 , H04B2201/70707
摘要： Reconstruction method for reconstructing a first signal (x(t)) regularly sampled at a sub-Nyquist rate, comprising the step of retrieving from the regularly spaced sampled values (y s [n], y(nT)) a set of weights (c n , c nr , c k ) and shifts (t n , t k ) with which said first signal (x(t) can be reconstructed. The reconstructed signal (x(t) can be represented as a sequence of known functions (γ(t) weighted by the weights (c k ) and shifted by the shifts (t k ). The sampling rate is at least equal to the rate of innovation (ρ) of the first signal (x(t)).
摘要翻译：一种用于重建以次奈奎斯特速率规则采样的第一信号（x（t））的重建方法，包括从规则间隔的采样值（y> s <[n]，y（nT））中检索一组可以重构所述第一信号（x（t））的权重（c> n <，c> nr <，c> k <）并移位（t> n <，t> k < t）可以表示为由权重（c> k <）加权并被移位（t> k <）的已知函数（gamma（t））的序列，采样率至少等于创新速率（x（t））的（rho）。

2. 发明授权

US06836237B2 Analog-to-digital converter 失效
公开(公告)号：US06836237B2
公开(公告)日：2004-12-28
申请号：US10806457
申请日：2004-03-23
申请人： Tadayuki Sakamoto
发明人： Tadayuki Sakamoto
IPC分类号： H03M112
CPC分类号： H03M1/14 , H03M1/365
摘要： In a converter which operates in a serial-parallel manner and performs analog-to-digital (A/D) conversion, the number of high bits is made more than half the entire number of bits, with the number of low bits is given by half the entire number of bits, thereby acquiring high-bit and low-bit data. When no match exists between the high-bit data and the low-bit data, the high-bit data can be modified by means of the low-bit data.

3. 发明授权

US06831585B2 Distributed averaging analog to digital converter topology 失效
标题翻译：分布式平均模数转换器拓扑
公开(公告)号：US06831585B2
公开(公告)日：2004-12-14
申请号：US10684444
申请日：2003-10-15
申请人： Jan Mulder , Christopher Michael Ward
发明人： Jan Mulder , Christopher Michael Ward
IPC分类号： H03M112
CPC分类号： H03K17/04106 , H03M1/0646 , H03M1/146 , H03M1/204 , H03M1/206 , H03M1/361 , H03M1/365
摘要： An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
摘要翻译：模数转换器包括连接到参考梯形图的抽头的第一放大器阵列，第二放大器阵列，其中第一放大器阵列中的每个放大器仅连接到第二放大器阵列的两个放大器，第三放大器阵列，其中每个第二放大器阵列中的放大器仅连接到第三放大器阵列的两个放大器，以及连接到第三放大器阵列的输出的编码器，其将输出转换为N位数字信号。

4. 发明授权

US06831584B2 High-speed low-distortion analog-to digital converter 有权
公开(公告)号：US06831584B2
公开(公告)日：2004-12-14
申请号：US10645924
申请日：2003-08-22
申请人： Xicheng Jiang , Zhengyu Wang , Frank Chang
发明人： Xicheng Jiang , Zhengyu Wang , Frank Chang
IPC分类号： H03M112
CPC分类号： H03M1/0646 , H03M1/361
摘要： An analog to digital converter includes an array of differential input amplifiers. Each amplifier inputs an input voltage and a corresponding voltage reference, and outputs a differential signal representing a comparison of the input voltage and the corresponding voltage reference. A plurality of latches stores the differential signal from each of the differential input amplifiers. A decoder converts the stored differential signals to N-bit digital output. A first interface amplifier is connected to a first edge amplifier of the array through a first cross point. A second interface amplifier is connected to a second edge amplifier of the array through a second cross point. The first interface amplifier and the second interface amplifier are connected to each other through a third cross point.

5. 发明授权

US06822599B2 Integrated circuit and A/D conversion circuit 有权
公开(公告)号：US06822599B2
公开(公告)日：2004-11-23
申请号：US10731114
申请日：2003-12-10
申请人： Masato Yoshioka , Kunihiko Gotoh , Hiroshi Yamazaki , Masahiro Kudo , Hiroyuki Nakamoto
发明人： Masato Yoshioka , Kunihiko Gotoh , Hiroshi Yamazaki , Masahiro Kudo , Hiroyuki Nakamoto
IPC分类号： H03M112
CPC分类号： H03M1/069 , H03M1/0682 , H03M1/145
摘要： The integrated circuit comprises an interior division circuit to hold a first amount of charge corresponding to a weighted sum of a first analog voltage and a second analog voltage corresponding to a digital signal, an exterior division circuit to hold a second amount of charge corresponding to a difference between the first analog voltage and second analog voltage, and an amplifying circuit to generate a voltage not within the range between the first analog voltage and the second analog voltage by amplifying the voltage depending on the sum of the first amount of charge and the second amount of charge. The integrated circuit may provide a lower consumption and small area integrated circuit which can generate an exterior division voltage of higher accuracy.

6. 发明授权

US06816104B1 Analog-to-digital converter utilizing a timer for increased resolution 失效
标题翻译：模数转换器利用定时器提高分辨率
公开(公告)号：US06816104B1
公开(公告)日：2004-11-09
申请号：US10604359
申请日：2003-07-14
申请人： Chi-Cheng Lin
发明人： Chi-Cheng Lin
IPC分类号： H03M112
CPC分类号： H03M1/007 , H03M1/56
摘要： An analog-to-digital converter includes a capacitor for storing charge and a current source for flowing current through the capacitor for charging the capacitor. The analog-to-digital converter also contains a switch for controlling flow of current from the current source to the capacitor, a comparator for outputting a first comparison value when an analog input voltage is approximately equal to a voltage across the capacitor, and a timer for calculating a charging period of time needed for the voltage across the capacitor to become equal to the analog input voltage. A controller is used for controlling operation of the switch, for starting the timer when the switch electrically connects the current source to the capacitor for charging the capacitor, for stopping the timer when the comparator outputs the first comparison value, and for converting the charging period of time calculated by the timer into a digital output voltage.
摘要翻译：模数转换器包括用于存储电荷的电容器和用于使电流流过用于对电容器充电的电容器的电流源。模数转换器还包括用于控制从电流源到电容器的电流的开关的开关，用于当模拟输入电压近似等于电容器两端的电压时输出第一比较值的比较器，以及定时器用于计算电容器两端的电压所需的充电时间段变得等于模拟输入电压。控制器用于控制开关的操作，用于当开关将电流源电连接到用于对电容器充电的电容器时启动定时器，当比较器输出第一比较值时停止定时器，并且用于转换充电周期的时间由计时器计算成数字输出电压。

7. 发明授权

US06816101B2 High-speed analog-to-digital converter using a unique gray code 失效
标题翻译：高速模数转换器采用独特的灰度代码
公开(公告)号：US06816101B2
公开(公告)日：2004-11-09
申请号：US10383703
申请日：2003-03-07
申请人： Vincent Mark Hietala , Andrew Joo Kim
发明人： Vincent Mark Hietala , Andrew Joo Kim
IPC分类号： H03M112
CPC分类号： H03M1/0687 , H03M1/0809 , H03M1/361 , H03M7/16 , H04B14/02
摘要： A method for high speed communications uses an inventive Q-Gray code. The Q-Gray code simplifies the hardware needed to convert analog Q-Gray code signals to digital signals. An analog-to-digital converter can use a plurality of comparators for receiving the multilevel signal and a plurality of decoder blocks coupled to comparators for decoding the multilevel signal. Each decoder block can include an equal number of inputs. Specifically, each decoder block can also include a parity detector with an equal number of inputs. Each decoder block can also employ a bank of identical parity detectors relative to another decoder block. Each comparator of the analog to digital converter can have an individually or externally adjustable (or both) threshold level.

8. 发明授权

US06803870B2 Procedure and device for analog-to-digital conversion 有权
标题翻译：用于模数转换的程序和设备
公开(公告)号：US06803870B2
公开(公告)日：2004-10-12
申请号：US10642730
申请日：2003-08-19
申请人： Franz Kuttner
发明人： Franz Kuttner
IPC分类号： H03M112
CPC分类号： H03M3/39 , H03M3/424 , H03M3/426 , H03M3/436
摘要： During A/D conversion of time-discrete analog input values, a quantizer is used in which an analog quantization error is obtained after every conversion. The quantization error is stored in a buffer, and fed back through a subtracter to at least one input value of a subsequent conversion. The quantizer has a conversion frequency, which is more than double the maximum frequency contained in input values, so the conversion operates in an oversampling mode. During feedback the quantization errors of several conversions, prior to a varying number of conversions, are preferably fed back to an input value. The invention can be used with all conventional quantizers, for which an analog quantization error can be obtained, so it is possible through a noise shaping procedure to shift quantization noise into higher-frequency spectral ranges to improve the signal-to-noise ratio or reduce the quantization noise in a useful spectral range.
摘要翻译：在时间离散模拟输入值的A / D转换期间，使用量化器，其中在每次转换之后获得模拟量化误差。量化误差被存储在缓冲器中，并通过减法器反馈到后续转换的至少一个输入值。量化器具有转换频率，其大小是输入值中包含的最大频率的两倍，因此转换工作在过采样模式。在反馈期间，在不同数目的转换之前的几个转换的量化误差优选地被反馈到输入值。本发明可以与可以获得模拟量化误差的所有常规量化器一起使用，因此可以通过噪声整形过程将量化噪声转换为更高频率的频谱范围来提高信噪比或减小在有用的光谱范围内的量化噪声。

9. 发明授权

US06798370B1 Parallel A/D converter 失效
标题翻译：并行A / D转换器
公开(公告)号：US06798370B1
公开(公告)日：2004-09-28
申请号：US10418299
申请日：2003-04-18
申请人： Koichi Nagano
发明人： Koichi Nagano
IPC分类号： H03M112
CPC分类号： H03M1/004 , H03M1/002 , H03M1/185 , H03M1/367
摘要： A parallel A/D converter includes: a reference-voltage generation circuit for outputting m reference voltages (“m” is an integer of not less than two), each having different voltage values, in response to the bit precision of digital output signals; n comparators (“n” is an integer smaller than “m”); and an encoder for encoding outputs of the n comparators to output the digital output signals. Each of the n comparators compares the magnitude of one of the m reference voltages with that of an analog input signal. Thereby, power consumption can be reduced.
摘要翻译：并行A / D转换器包括：基准电压产生电路，用于响应于数字输出信号的位精度，输出m个参考电压（“m”为不小于2的整数），每个参考电压具有不同的电压值; n个比较器（“n”是小于“m”的整数）; 以及用于编码n个比较器的输出以输出数字输出信号的编码器。 n个比较器中的每个比较器将m个参考电压之一的幅度与模拟输入信号的幅度进行比较。从而能够降低功耗。

10. 发明授权

US06795010B1 Techniques for pausing and resuming analog-to-digital signal conversion 失效
标题翻译：暂停和恢复模数转换信号的技术
公开(公告)号：US06795010B1
公开(公告)日：2004-09-21
申请号：US10629390
申请日：2003-07-29
申请人： Yasho Potlapalli , Octavian Beldiman , Takashi Fujita
发明人： Yasho Potlapalli , Octavian Beldiman , Takashi Fujita
IPC分类号： H03M112
CPC分类号： H03M1/1225 , G06F3/05
摘要： Techniques are described for analog-to-digital signal conversion. According to exemplary embodiments, a first request is associated with a plurality of input terminals and a second request is associated with one of the input terminals. An analog signal presented at each of a portion of the input terminals associated with the first request is converted in succession into a digital value until the one of the input terminals associated with the second request is reached. A predetermined amount of time is waited to receive the second request. An analog signal presented at each of a remaining portion of the input terminals associated with the first request is converted in succession into a digital value when one of an expiration of the predetermined amount of time and a receiving of the second request occurs.
摘要翻译：描述了用于模数转换的技术。根据示例性实施例，第一请求与多个输入终端相关联，并且第二请求与输入终端之一相关联。在与第一请求相关联的输入端的一部分中的每一个处呈现的模拟信号被连续地转换为数字值，直到达到与第二请求相关联的输入端之一。等待预定时间量接收第二请求。当预定时间量的到期和第二个请求的接收发生之一时，呈现在与第一请求相关联的输入终端的剩余部分中的每一个处的模拟信号被连续地转换成数字值。

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