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1. 发明授权

US06277198B1 Use of tapered shadow clamp ring to provide improved physical vapor deposition system 失效
标题翻译：使用锥形阴影夹环提供改进的物理气相沉积系统
公开(公告)号：US06277198B1
公开(公告)日：2001-08-21
申请号：US09326395
申请日：1999-06-04
申请人： Tse-Yong Yao , Allen Thompson , Peijun Ding , Richard Hong
发明人： Tse-Yong Yao , Allen Thompson , Peijun Ding , Richard Hong
IPC分类号： B05C1300
CPC分类号： H01L21/68721 , C23C14/042 , C23C16/042 , C23C16/4585 , Y10T24/44983
摘要： A method and apparatus is provided for clamping and shielding the edge of a substrate useful in electronic device fabrication. A shadow ring is formed by an inward radial extension of the top surface of a generally annular shaped clamp ring. The shadow ring portion overhangs but does not contact the top surface of a substrate being processed. A smoothly tapered substrate contact surface extending from the outer diametrical extent of the shadow ring bottom surface to the bottom surface of the clamp ring is sized and adapted to engage the outer edge of a substrate. The substrate contact surface aligns the clamp ring to a substrate support member and a substrate to the substrate support member and the clamp ring as the substrate is lifted vertically.
摘要翻译：提供了用于夹持和屏蔽用于电子器件制造的衬底的边缘的方法和装置。阴影环由大致环形的夹环的顶表面的向内径向延伸形成。阴影环部分突出但不接触被处理的基底的顶表面。从阴影环底表面的外径范围延伸到夹紧环的底表面的平滑的锥形衬底接触表面的尺寸和尺寸适于接合衬底的外边缘。当衬底垂直提升时，衬底接触表面将夹紧环对准衬底支撑构件和衬底到衬底支撑构件和夹紧环。

2. 发明授权

US06328871B1 Barrier layer for electroplating processes 有权
标题翻译：电镀工艺的屏障层
公开(公告)号：US06328871B1
公开(公告)日：2001-12-11
申请号：US09375167
申请日：1999-08-16
申请人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
发明人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
IPC分类号： C23C2800
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76877
摘要： The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.
摘要翻译：本发明通常提供了一种用于制备用于电化学沉积的表面的方法，其包括在表面上形成高导电阻挡层并在高导电阻挡层上沉积种子层。本发明的另一方面提供了一种用于在基板上填充结构的方法，包括在所述结构的一个或多个表面上沉积高电导阻挡层，在所述阻挡层上沉积晶种层，以及电化学沉积金属以填充所述结构。

3. 发明授权

US06790776B2 Barrier layer for electroplating processes 有权
标题翻译：电镀工艺的屏障层
公开(公告)号：US06790776B2
公开(公告)日：2004-09-14
申请号：US10016255
申请日：2001-12-10
申请人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
发明人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
IPC分类号： C23C1434
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76877
摘要： The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.
摘要翻译：本发明通常提供了一种用于制备用于电化学沉积的表面的方法，其包括在表面上形成高导电阻挡层并在高导电阻挡层上沉积种子层。本发明的另一方面提供一种用于在衬底上填充结构的方法，包括在所述结构的一个或多个表面上沉积高电导阻挡层，在所述阻挡层上沉积晶种层，以及电化学沉积金属以填充所述结构。

4. 发明申请

US20050031784A1 Barrier layer for electroplating processes 审中-公开
标题翻译：电镀工艺的屏障层
公开(公告)号：US20050031784A1
公开(公告)日：2005-02-10
申请号：US10931865
申请日：2004-09-01
申请人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
发明人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
IPC分类号： C25D5/34 , C25D3/00 , C25D7/12 , H01L21/28 , H01L21/288 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , C23C14/00 , H05H1/24
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76877
摘要： The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.
摘要翻译：本发明通常提供了一种用于制备用于电化学沉积的表面的方法，其包括在表面上形成高导电阻挡层并在高导电阻挡层上沉积种子层。本发明的另一方面提供了一种用于在基板上填充结构的方法，包括在所述结构的一个或多个表面上沉积高电导阻挡层，在所述阻挡层上沉积晶种层，以及电化学沉积金属以填充所述结构。

5. 发明授权

US06607640B2 Temperature control of a substrate 失效
标题翻译：基板的温度控制
公开(公告)号：US06607640B2
公开(公告)日：2003-08-19
申请号：US09538343
申请日：2000-03-29
申请人： Arvind Sundarrajan , Darryl Angelo , Tse-Yong Yao , Peijun Ding
发明人： Arvind Sundarrajan , Darryl Angelo , Tse-Yong Yao , Peijun Ding
IPC分类号： C23C1434
CPC分类号： C23C14/541
摘要： A method of improving the temperature control of a clamped substrate mounted on a substrate support that is biased, the substrate support having a passage therethrough to permit a flow of backside gas for heating or cooling the substrate, whereby the pressure of the backside gas is maintained at at least 15 torr. A high gas pressure improves the thickness uniformity of processing across the substrate. For plasma deposition of sputtered seed layers, the morphology of the seed layer is improved near the edge of the substrate and the uniformity of the layer across the substrate is also improved.
摘要翻译：一种改进安装在被偏压的衬底支撑件上的夹持衬底的温度控制的方法，衬底支撑件具有穿过其中的通道，以允许背面气体流动以加热或冷却衬底，从而维持背侧气体的压力至少15托。高气体压力提高了跨衬底的加工厚度均匀性。对于溅射种子层的等离子体沉积，种子层的形态在衬底的边缘附近得到改善，并且跨衬底的层的均匀性也得到改善。

6. 发明授权

US06217721B1 Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer 失效
标题翻译：填充狭窄的孔径并与金属形成互连，利用晶体取向的衬层
公开(公告)号：US06217721B1
公开(公告)日：2001-04-17
申请号：US08628835
申请日：1996-04-05
申请人： Zheng Xu , John Forster , Tse-Yong Yao , Jaim Nulman , Fusen Chen
发明人： Zheng Xu , John Forster , Tse-Yong Yao , Jaim Nulman , Fusen Chen
IPC分类号： C23C1434
CPC分类号： H01L21/2855 , C23C14/0036 , C23C14/046 , C23C14/0641 , C23C14/32 , C23C14/358 , H01J37/34 , H01J2237/32 , H01L21/28518 , H01L21/76846 , H01L21/76876 , H01L21/76877 , H01L21/76882 , H01L23/485 , H01L23/5226 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An aluminum sputtering process, particularly useful for filling vias and contacts of high aspect ratios formed through a dielectric layer and also usefull for forming interconnects that are highly resistant to electromigration. A liner or barrier layer is first deposited by a high-density plasma (HDP) physical vapor deposition (PVD, also called sputtering) process, such as is done with an inductively coupled plasma. If a contact is connected at its bottom to a silicon element, the first sublayer of the liner layer is a Ti layer, which is silicided to the silicon substrate. The second sublayer comprises TiN, which not only acts as a barrier against the migration of undesirable components into the underlying silicon but also when deposited with an HDP process and biased wafer forms a dense, smooth crystal structure. The third sublayer comprises Ti and preferably is graded from TiN to Ti. Over the liner layer, an aluminum layer is deposited in a standard, non-HDP process. The liner layer allows the hottest part of the aluminum deposition to be performed at a relatively low temperature between 320 and 500° C., preferably between 350 and 420° C., while still filling narrow plug holes, and the TiN does not need to be annealed to form an effective barrier against diffusion into the silicon. A horizontal interconnect formed by the inventive process is resistant to electromigration.
摘要翻译：铝溅射工艺，特别适用于填充通过电介质层形成的高纵横比的通孔和触点，并且也可用于形成高度抵抗电迁移的互连。衬垫或阻挡层首先通过高密度等离子体（HDP）物理气相沉积（PVD，也称为溅射）工艺沉积，例如用电感耦合等离子体进行。如果接触件的底部连接到硅元件，衬垫层的第一子层是Ti层，硅层被硅化到硅衬底。第二子层包括TiN，其不仅用作防止不期望的组分迁移到下面的硅中的阻挡层，而且当用HDP工艺沉积并且偏置的晶片形成致密的，平滑的晶体结构时。第三子层包含Ti，优选从TiN到Ti分级。在衬里层上，铝层以标准的非HDP工艺沉积。衬垫层允许铝沉积的最热部分在320和500℃之间的较低温度下进行，优选在350和420℃之间，同时仍然填充窄的塞孔，并且TiN不需要进行退火以形成抵抗硅中扩散的有效屏障。由本发明方法形成的水平互连对于电迁移是耐受的。

7. 发明授权

US06313027B1 Method for low thermal budget metal filling and planarization of contacts vias and trenches 失效
标题翻译：用于低热预算金属填充和平面化接触通孔和沟槽半导体晶片的方法和装置
公开(公告)号：US06313027B1
公开(公告)日：2001-11-06
申请号：US08944140
申请日：1997-10-06
申请人： Zheng Xu , John Forster , Tse-Yong Yao
发明人： Zheng Xu , John Forster , Tse-Yong Yao
IPC分类号： H01L214763
CPC分类号： H01L21/2855 , C23C14/0036 , C23C14/046 , C23C14/0641 , C23C14/32 , C23C14/358 , H01J37/34 , H01J2237/32 , H01L21/28518 , H01L21/76846 , H01L21/76876 , H01L21/76877 , H01L21/76882 , H01L23/485 , H01L23/5226 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact. The carrier layer preferably comprises a layer formed by ionizing the flux of sputter deposition material, partially reacting the flux with a gas, and depositing the resulting material on a substrate.
摘要翻译：本发明涉及载体层和由载体层实现的接触，其能够在多层集成电路通孔，通孔或沟槽中制造具有类似熔点的铝（包括铝合金和具有相似熔点的其它导电材料）电接触，所述多层集成电路通孔，通孔或沟槽具有长宽比大于1。事实上，已经显示了这种结构能够使通孔，通孔和沟槽中的这种接触制造具有高达至少5:1的纵横比，并且应该能够填充具有高达约12:1的纵横比的孔。除了允许以高纵横比形成导电接触之外，载体层提供了扩散阻挡层，其防止铝迁移到与电触点一起操作的周围基底材料中。载体层优选包括通过电离溅射沉积材料的焊剂形成的层，使焊剂与气体部分地反应，并将所得材料沉积在衬底上。

8. 发明授权

US6051114A Use of pulsed-DC wafer bias for filling vias/trenches with metal in HDP physical vapor deposition 失效
标题翻译：在HDP物理气相沉积中使用脉冲直流晶片偏置来填充金属通孔/沟槽
公开(公告)号：US6051114A
公开(公告)日：2000-04-18
申请号：US880467
申请日：1997-06-23
申请人： Tse-Yong Yao , Zheng Xu , Kenny King-tai Ngan , Xing Chen , John Urbahn , Lawrence P. Bourget
发明人： Tse-Yong Yao , Zheng Xu , Kenny King-tai Ngan , Xing Chen , John Urbahn , Lawrence P. Bourget
IPC分类号： C23C14/04 , C23C14/34 , C23C14/35 , H01J37/32 , H01L21/768
CPC分类号： H01L21/2855 , C23C14/046 , C23C14/34 , C23C14/357 , H01J37/32623 , H01J37/32678 , H01J37/32706 , H01J37/34 , H01L21/76877
摘要： The present invention provides a method and apparatus for preferential PVD conductor fill in an integrated circuit structure. The present invention utilizes a high density plasma for sputter deposition of a conductive layer on a patterned substrate, and a pulsed DC power source capacitively coupled to the substrate to generate an ion current at the surface of the substrate. The ion current prevents sticking of the deposited material to the field areas of the patterned substrate, or etches deposited material from the field areas to eliminate crowning or cusping problems associated with deposition of a conductive material in a trench, hole or via formed on the substrate.
摘要翻译：本发明提供了一种用于集成电路结构中优先PVD导体填充的方法和装置。本发明利用高密度等离子体在图案化衬底上溅射沉积导电层，以及电容耦合到衬底的脉冲DC电源，以在衬底的表面产生离子电流。离子电流防止沉积的材料粘附到图案化衬底的场区域，或者蚀刻从场区域沉积的材料，以消除与在衬底上形成的沟槽，孔或通孔中的导电材料的沉积相关的凸起或弯曲问题。

9. 发明授权

US6140235A High pressure copper fill at low temperature 失效
标题翻译：高压铜填充低温
公开(公告)号：US6140235A
公开(公告)日：2000-10-31
申请号：US985844
申请日：1997-12-05
申请人： Tse-Yong Yao , Barry Chin
发明人： Tse-Yong Yao , Barry Chin
IPC分类号： H01L21/00 , H01L21/768 , H01L21/44
CPC分类号： H01L21/67167 , H01L21/67184 , H01L21/6719 , H01L21/67207 , H01L21/76882
摘要： The present invention provides a method and apparatus for filling submicron features on a substrate with a polycrystalline metal such as copper or a copper alloy comprising at least 90% by weight of copper. The method comprises deposition of a polycrystalline metal layer which bridges the submicron features and has a grain size smaller than the submicron features, and exposing the polycrystalline metal layer to a high pressure processing gas at a temperature less than one half of the absolute melting temperature to extrude the metal layer into the submicron features.
摘要翻译：本发明提供了一种用多晶金属（例如铜或铜合金）在基底上填充亚微米特征的方法和装置，其包含至少90重量％的铜。该方法包括沉积桥接亚微米特征并具有小于亚微米特征的晶粒尺寸的多晶金属层，并将多晶金属层暴露于高于绝对熔融温度的一半的温度下的高压处理气体，至将金属层挤压成亚微米特征。

10. 发明授权

US06436302B1 Post CU CMP polishing for reduced defects 失效
标题翻译：后CU CMP抛光减少缺陷
公开(公告)号：US06436302B1
公开(公告)日：2002-08-20
申请号：US09492267
申请日：2000-01-27
申请人： Juy-Lung Li , Tse-Yong Yao , Fred C. Redeker , Rajeev Bajaj , Yutao Ma
发明人： Juy-Lung Li , Tse-Yong Yao , Fred C. Redeker , Rajeev Bajaj , Yutao Ma
IPC分类号： H01L21463
CPC分类号： H01L21/7684 , H01L21/02074 , H01L21/3212
摘要： Cu metallization is treated to reduce defects and effect passivation, and to reduce leakage between lines, by removing surface defects subsequent to CMP and barrier layer removal. Embodiments include the sequential steps of: CMP and barrier layer removal; buffing with a solution comprising citric acid, ammonium hydroxide and deionized water to remove copper oxide; rinsing with deionized water or an inhibitor solution, e.g., benzotriazole or 5-methyl triazole in deionized water; buffing with an abrasive slurry; and rinsing with deionized water or an inhibitor solution.
摘要翻译：处理Cu金属化以减少缺陷并实现钝化，并通过去除CMP和阻挡层去除之后的表面缺陷来减少线之间的泄漏。实施例包括顺序步骤：CMP和阻挡层去除; 用包含柠檬酸，氢氧化铵和去离子水的溶液抛光以除去氧化铜; 用去离子水或抑制剂溶液（例如苯并三唑或5-甲基三唑）在去离子水中冲洗; 用磨料浆抛光; 并用去离子水或抑制剂溶液冲洗。

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