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1. 发明授权

US08440376B2 Exposure determining method, method of manufacturing semiconductor device, and computer program product 有权
标题翻译：曝光确定方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US08440376B2
公开(公告)日：2013-05-14
申请号：US13007238
申请日：2011-01-14
申请人： Toshiya Kotani , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
发明人： Toshiya Kotani , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： G03F7/70425 , G03F7/70558
摘要： According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.
摘要翻译：根据一个实施例，获取形成在掩模上的掩模图案与期望的掩模图案之间的二维形状参数的偏差量分布作为掩模图案图。使得当在掩模经受曝光拍摄以形成基板上的图案和在基板上形成图案之后形成的基板上的图案之间的二维形状参数的偏移量适合在预定范围内时，确定曝光基于掩模图案图，在基板上形成图案的曝光中的每个位置。

2. 发明申请

US20100241261A1 PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：图案生成方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US20100241261A1
公开(公告)日：2010-09-23
申请号：US12705640
申请日：2010-02-15
申请人： Takafumi TAGUCHI , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
发明人： Takafumi TAGUCHI , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
IPC分类号： G05B13/04 , G06F17/50 , G06F19/00
CPC分类号： G03F1/36
摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.
摘要翻译：基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据执行模式形成模拟。根据模拟结果提取的风险点计算过程条件的最差条件。改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度小于模拟结果。

3. 发明授权

US08266552B2 Pattern generating method, method of manufacturing semiconductor device, and recording medium 有权
标题翻译：图案生成方法，制造半导体器件的方法和记录介质
公开(公告)号：US08266552B2
公开(公告)日：2012-09-11
申请号：US12705640
申请日：2010-02-15
申请人： Takafumi Taguchi , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
发明人： Takafumi Taguchi , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
IPC分类号： G06F17/50 , G06F19/00 , G05B13/04
CPC分类号： G03F1/36
摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.
摘要翻译：基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据来执行模式形成模拟。根据模拟结果提取的风险点计算过程条件的最差条件。改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度小于模拟结果。

4. 发明申请

US20100216064A1 SEMICONDUCTOR-DEVICE MANUFACTURING METHOD, COMPUTER PROGRAM PRODUCT, AND EXPOSURE-PARAMETER CREATING METHOD 审中-公开
标题翻译：半导体器件制造方法，计算机程序产品和曝光参数创建方法
公开(公告)号：US20100216064A1
公开(公告)日：2010-08-26
申请号：US12683943
申请日：2010-01-07
申请人： Michiya Takimoto , Hiromitsu Mashita , Toshiya Kotani
发明人： Michiya Takimoto , Hiromitsu Mashita , Toshiya Kotani
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70441 , G03F1/70 , G03F7/70525
摘要： A semiconductor-device manufacturing method includes: correcting a systematic component of process proximity effect, which occurs in a process other than exposure processing to thereby set a target pattern after exposure; adjusting an exposure parameter such that a difference between a dimension of the target pattern and a pattern dimension after the exposure is within tolerance; and forming, when an exposure margin calculated from the exposure parameter by using the exposure the random component of fluctuation in the process proximity effect is within the tolerance, a pattern on a semiconductor substrate with the adjusted exposure parameter.
摘要翻译：半导体器件制造方法包括：校正在曝光处理之外的处理中发生的过程接近效应的系统分量，从而在曝光之后设置目标图案; 调整曝光参数，使得目标图案的尺寸与曝光后的图案尺寸之间的差在公差之内; 并且当通过使用曝光从曝光参数计算出的曝光余量时，在处理接近效应中的随机波动分量在容差内的情况下，形成具有调整曝光参数的半导体衬底上的图案。

5. 发明授权

US08196071B2 Creating mask data of integrated circuit patterns using calculated etching conversion difference 失效
标题翻译：使用计算出的蚀刻转换差异创建集成电路图案的掩模数据
公开(公告)号：US08196071B2
公开(公告)日：2012-06-05
申请号：US12688644
申请日：2010-01-15
申请人： Hiromitsu Mashita , Katsumi Iyanagi , Takafumi Taguchi , Toshiya Kotani , Hidefumi Mukai , Taiga Uno , Takashi Nakazawa
发明人： Hiromitsu Mashita , Katsumi Iyanagi , Takafumi Taguchi , Toshiya Kotani , Hidefumi Mukai , Taiga Uno , Takashi Nakazawa
IPC分类号： G06F17/50
CPC分类号： G03F1/80 , G03F1/36 , G03F1/54
摘要： A pattern data creating method comprising: referring to a first correspondence relation between an amount of dimension variation between a first pattern formed on a substrate and a second pattern formed by processing the substrate using the first pattern and either one of a pattern total surface area and a pattern boundary length of the first pattern; and creating pattern data for forming the first pattern.
摘要翻译：一种图形数据生成方法，包括：参照形成在基板上的第一图案和通过使用第一图案处理基板而形成的第二图案之间的尺寸变化量之间的第一对应关系，以及图案总表面积和第一图案的图案边界长度; 以及创建用于形成第一图案的图案数据。

6. 发明申请

US20100185313A1 PATTERN DATA CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
标题翻译：图形数据创建方法，计算机程序产品和半导体器件制造方法
公开(公告)号：US20100185313A1
公开(公告)日：2010-07-22
申请号：US12688644
申请日：2010-01-15
申请人： Hiromitsu MASHITA , Katsumi Iyanagi , Takafumi Taguchi , Toshiya Kotani , Hidefumi Mukai , Taiga Uno , Takashi Nakazawa
发明人： Hiromitsu MASHITA , Katsumi Iyanagi , Takafumi Taguchi , Toshiya Kotani , Hidefumi Mukai , Taiga Uno , Takashi Nakazawa
IPC分类号： G06F17/50
CPC分类号： G03F1/80 , G03F1/36 , G03F1/54
摘要： A pattern data creating method comprising: referring to a first correspondence relation between an amount of dimension variation between a first pattern formed on a substrate and a second pattern formed by processing the substrate using the first pattern and either one of a pattern total surface area and a pattern boundary length of the first pattern; and creating pattern data for forming the first pattern.
摘要翻译：一种图形数据生成方法，包括：参照形成在基板上的第一图案和通过使用第一图案处理基板而形成的第二图案之间的尺寸变化量之间的第一对应关系，以及图案总表面积和第一图案的图案边界长度; 以及创建用于形成第一图案的图案数据。

7. 发明申请

US20100202181A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20100202181A1
公开(公告)日：2010-08-12
申请号：US12561531
申请日：2009-09-17
申请人： Takaki HASHIMOTO , Hidefumi Mukai , Yasunobu Kai , Toshiya Kotani
发明人： Takaki HASHIMOTO , Hidefumi Mukai , Yasunobu Kai , Toshiya Kotani
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C5/025
摘要： A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction.
摘要翻译：半导体存储器件包括形成有存储单元的半导体衬底。互连件沿着半导体衬底上方的第一方向布置，并且沿着垂直于第一方向的第二方向具有规则的间隔。互连触点连接互连和半导体衬底，布置在三行或更多行上。连接到在第二方向相邻的互连件的两个互连触点中的每一个的中心沿着第一方向彼此偏离。

8. 发明授权

US07713833B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07713833B2
公开(公告)日：2010-05-11
申请号：US12557111
申请日：2009-09-10
申请人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
IPC分类号： H01L21/76
CPC分类号： H01L27/11524 , H01L21/0337 , H01L21/32139
摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.
摘要翻译：根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。

9. 发明申请

US20080320434A1 PHOTOMASK MANAGEMENT METHOD AND PHOTOMASK WASH LIMIT GENERATING METHOD 有权
标题翻译：光电管理方法和照相机限流发生方法
公开(公告)号：US20080320434A1
公开(公告)日：2008-12-25
申请号：US12112688
申请日：2008-04-30
申请人： Hidefumi MUKAI , Shinji Yamaguchi , Yukiyasu Arisawa , Toshiya Kotani
发明人： Hidefumi MUKAI , Shinji Yamaguchi , Yukiyasu Arisawa , Toshiya Kotani
IPC分类号： G06F17/50 , G01B7/00
CPC分类号： G03F1/82 , G03F1/86
摘要： A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern previously determined for the photomask is measured. Lithography tolerance is derived by performing a lithography simulation for the measured two-dimensional shape by use of the measured physical amount. Then, whether the photomask can be used or not is determined based on the derived lithography tolerance.
摘要翻译：洗涤光掩模，并且测量光掩模的透光率和相位差的至少一个物理量，图案的尺寸，图案的高度和图案的侧壁形状。之后，测量先前为光掩模确定的边界图案的二维形状。通过使用测量的物理量对所测量的二维形状进行光刻模拟，导出光刻容限。然后，是否可以使用光掩模是基于导出的平版印刷公差来确定的。

10. 发明授权

US07941767B2 Photomask management method and photomask wash limit generating method 有权
标题翻译：光掩模管理方法和光掩模清洗极限生成方法
公开(公告)号：US07941767B2
公开(公告)日：2011-05-10
申请号：US12112688
申请日：2008-04-30
申请人： Hidefumi Mukai , Shinji Yamaguchi , Yukiyasu Arisawa , Toshiya Kotani
发明人： Hidefumi Mukai , Shinji Yamaguchi , Yukiyasu Arisawa , Toshiya Kotani
IPC分类号： G06F17/50 , G06F19/00 , G01B7/00 , G06K9/00
CPC分类号： G03F1/82 , G03F1/86
摘要： A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern previously determined for the photomask is measured. Lithography tolerance is derived by performing a lithography simulation for the measured two-dimensional shape by use of the measured physical amount. Then, whether the photomask can be used or not is determined based on the derived lithography tolerance.
摘要翻译：洗涤光掩模，并且测量光掩模的透光率和相位差的至少一个物理量，图案的尺寸，图案的高度和图案的侧壁形状。之后，测量先前为光掩模确定的边界图案的二维形状。通过使用测量的物理量对所测量的二维形状进行光刻模拟，导出光刻容限。然后，是否可以使用光掩模是基于导出的平版印刷公差来确定的。

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