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1. 发明授权

US06207493B1 Formation of out-diffused bitline by laser anneal 失效
公开(公告)号：US06207493B1
公开(公告)日：2001-03-27
申请号：US09136586
申请日：1998-08-19
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L21/2254 , H01L21/2257 , H01L21/268 , H01L21/743 , H01L27/10876
摘要： The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

2. 发明授权

US06333533B1 Trench storage DRAM cell with vertical three-sided transfer device 失效
标题翻译：沟槽存储DRAM单元，具有垂直三面传输设备
公开(公告)号：US06333533B1
公开(公告)日：2001-12-25
申请号：US09394964
申请日：1999-09-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.
摘要翻译：一对动态随机存取存储器单元，其有源区域的每个端部由三个侧面由栅极导体包围。由栅极导体围绕的有源区域的每个端部的宽度优选地小于由有源区域的该端部相交的深沟槽的宽度的百分之五十。

3. 发明授权

US06258661B1 Formation of out-diffused bitline by laser anneal 失效
标题翻译：通过激光退火形成扩散位线
公开(公告)号：US06258661B1
公开(公告)日：2001-07-10
申请号：US09651614
申请日：2000-08-30
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L21/2254 , H01L21/2257 , H01L21/268 , H01L21/743 , H01L27/10876
摘要： The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.
摘要翻译：本发明提供了通过利用其中沟槽区域中的掺杂剂材料扩散到半导体衬底中的激光退火步骤在半导体衬底中形成向外扩散位线的方法。外扩散位线也可以利用离子注入步骤形成。

4. 发明授权

US06376873B1 Vertical DRAM cell with robust gate-to-storage node isolation 失效
标题翻译：垂直DRAM单元具有鲁棒的栅极到存储节点隔离
公开(公告)号：US06376873B1
公开(公告)日：2002-04-23
申请号：US09287410
申请日：1999-04-07
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jeffrey J. Welser
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jeffrey J. Welser
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876
摘要： A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.
摘要翻译：形成在具有沟槽的衬底中的动态随机存取存储器件。沟槽具有侧壁，顶部，下部和圆周。该装置包括信号存储节点，该信号存储节点包括形成在沟槽下部的存储节点导体，并且通过节点电介质和节点电介质上方的环形氧化物与侧壁隔离。埋置的带子耦合到存储节点导体并且与套环氧化物上方的沟槽的侧壁的一部分接触。形成在掩埋带上的沟槽电介质具有沟槽顶部的介电厚度。信号传送装置包括：第一扩散区域，其延伸到与所述掩埋带接触的所述沟槽侧壁的所述部分相邻的所述衬底;门绝缘体，其具有形成在所述第一掩埋带的上方的所述沟槽侧壁上的栅绝缘体厚度，绝缘体厚度小于沟槽顶部电介质厚度，以及形成在沟槽顶部电介质并且邻近栅极绝缘体的沟槽内的栅极导体。

5. 发明授权

US08039334B2 Shared gate for conventional planar device and horizontal CNT 有权
标题翻译：常规平面器件和水平CNT的共用门
公开(公告)号：US08039334B2
公开(公告)日：2011-10-18
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

6. 发明授权

US08004024B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08004024B2
公开(公告)日：2011-08-23
申请号：US12348404
申请日：2009-01-05
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

7. 发明授权

US07557023B2 Implantation of gate regions in semiconductor device fabrication 失效
标题翻译：在半导体器件制造中植入栅极区域
公开(公告)号：US07557023B2
公开(公告)日：2009-07-07
申请号：US11532189
申请日：2006-09-15
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/425
CPC分类号： H01L29/66545 , H01L21/0273 , H01L21/266 , H01L21/28035 , H01L29/1083 , H01L29/6653 , H01L29/6659
摘要： A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.
摘要翻译：半导体制造方法。该方法包括提供半导体结构，其包括（i）半导体层，（ii）半导体层上的栅极电介质层，以及（iii）栅极电介质层上的栅电极区。栅极电介质层被夹在半导体层和栅极电极区域之间并使其电绝缘。半导体层和栅极介电层共享公共接口表面，其界定垂直于公共接口表面的参考方向并且从半导体层指向栅极介电层。接下来，在栅极电介质层和栅极电极区域上形成抗蚀剂层。接下来，去除在参考方向上正好在栅极区域上方的抗蚀剂层的盖部分，而不去除在参考方向上不在栅电极区域正上方的任何部分的抗蚀剂层。

8. 发明申请

US20090087795A1 METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM 失效
标题翻译：用于在浸没层析系统中清洁半导体衬底的方法和装置
公开(公告)号：US20090087795A1
公开(公告)日：2009-04-02
申请号：US12045290
申请日：2008-03-10
申请人： Steven J. Holmes , Mark C. Hakey , Toshiharu Furukawa , David V. Horak
发明人： Steven J. Holmes , Mark C. Hakey , Toshiharu Furukawa , David V. Horak
IPC分类号： G03F7/20
CPC分类号： G03F7/70341 , G03F7/70925
摘要： A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system.
摘要翻译：一种用于减少和防止残留物形成和去除在浸没式光刻工具中形成的残留物的方法和装置。该设备包括在浸没式光刻系统的浸没头部内并入清洁机构，或者在浸没式光刻系统的清洁站中包括清洁机构。

9. 发明授权

US07393779B2 Shrinking contact apertures through LPD oxide 失效
标题翻译：通过LPD氧化物收缩接触孔
公开(公告)号：US07393779B2
公开(公告)日：2008-07-01
申请号：US11163786
申请日：2005-10-31
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.
摘要翻译：通过电介质的亚光刻接触孔形成在电介质，硬掩模和含氧化物种子层的堆叠中。通过种子层的初始孔径通过液相沉积接收氧化物沉积，该相沉积选择性地粘附到种子层中的孔的暴露的垂直壁。通过所添加的材料的厚度减小尺寸的亚光刻孔径在硬掩模中限定了减小的孔径。缩小的硬掩模然后限定通过电介质的亚光刻孔。

10. 发明授权

US07368712B2 Y-shaped carbon nanotubes as AFM probe for analyzing substrates with angled topography 有权
标题翻译： Y型碳纳米管作为用于分析具有倾斜的地形的基底的AFM探针
公开(公告)号：US07368712B2
公开(公告)日：2008-05-06
申请号：US11164792
申请日：2005-12-06
申请人： Carol A. Boye , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Carol A. Boye , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： G01N23/00 , G21K7/00
CPC分类号： G01Q60/42 , G01Q70/12
摘要： A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the chemically modified carbon nanotube is modified with any of an amine, carboxyl, fluorine, and metallic component. Preferably, each of the pair of angled arms comprises a length of at least 200 nm and a diameter between 10 and 200 nm. Moreover, the chemically modified carbon nanotube is preferably adapted to allow differentiation between substrate materials to be probed. Additionally, the chemically modified carbon nanotube is preferably adapted to allow fluorine gas to flow through the chemically modified carbon nanotube onto a substrate to be characterized. Furthermore, the chemically modified carbon nanotube is preferably adapted to chemically react with a substrate surface to be characterized.
摘要翻译： Y型碳纳米管原子力显微镜探针头和方法包括轴部分; 一对成角度的臂，其从所述轴部的同一端延伸，其中所述轴部和所述一对成角度的臂包括化学改性的碳纳米管，并且其中所述化学改性的碳纳米管用胺，羧基，氟，和金属成分。优选地，一对成角度的臂中的每一个包括至少200nm的长度和10和200nm之间的直径。此外，化学改性的碳纳米管优选适于允许待探测的基底材料之间的分化。此外，化学改性的碳纳米管优选适于使氟气通过化学改性的碳纳米管流动到待表征的基底上。此外，化学改性的碳纳米管优选适于与要表征的基材表面发生化学反应。

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