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1. 发明专利

JP2006080129A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006080129A
公开(公告)日：2006-03-23
申请号：JP2004259534
申请日：2004-09-07
申请人： Toshiba Corp , 株式会社東芝
发明人： OTANI NORIO , IIZUKA HIROHISA , HAZAMA HIROAKI , NARITA KAZUHITO , KAMIYA EIJI
IPC分类号： H01L27/10 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To prevent a silicon substrate from being cut due to etching of counter-boring of an STI for increased reliability of a memory cell without increasing the number of photolithography steps.
SOLUTION: Silicon oxide films 13, 25 and 26 as a gate insulating film and gate electrodes 6, 7 12a, and 12b such as a memory cell transistor 1 or the like are formed on a silicon substrate 3 (refer to (a) and (b).). A silicon oxide film 19 is formed on the entire surface of a cell to ensure the reliability of the cell, and it is peeled off from a contact surface and the surface of the gate electrode 12b of a high breakdown strength transistor 9. In this case, the silicon oxide film 26 as the gate insulating film and the STI 10 are etched at the same time.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止硅衬底由于蚀刻用于提高存储单元可靠性的STI的反向钻削而被切割，而不增加光刻步骤的数量。解决方案：在硅衬底3上形成作为栅绝缘膜的氧化硅膜13,25和26以及诸如存储单元晶体管1等的栅电极6,7 12a和12b（参见（a ）和（b））。在电池的整个表面上形成氧化硅膜19，以确保电池的可靠性，并且从接触表面和高击穿强度晶体管9的栅电极12b的表面剥离。在这种情况下，作为栅极绝缘膜的氧化硅膜26和STI 10同时被蚀刻。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2004363443A Non-volatile semiconductor storage device and its manufacturing method 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2004363443A
公开(公告)日：2004-12-24
申请号：JP2003162019
申请日：2003-06-06
申请人： Toshiba Corp , 株式会社東芝
发明人： HAZAMA HIROAKI , MORI SEIICHI , IIZUKA HIROHISA , OTANI NORIO , NARITA KAZUHITO
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device and its manufacturing method capable of shallowly controlling channel profiles, improving the controllability of impurity profiles, and performing the microfabrication of elements.
SOLUTION: The non-volatile semiconductor storage device including at least one MOS transistor in a peripheral circuit is provided with a semiconductor substrate 20, element separation insulating films 34 buried in element separation grooves 33 formed on the semiconductor substrate 20 to form a plurality of element forming areas, floating gates 26, 29 formed in respective element forming areas through a 1st gate insulating film 25, a control gate 37 formed on the floating gates 26, 29 through a 2nd gate insulating film 35, and source-drain areas 40 formed on the semiconductor substrate 20 by self-matching with the control gate 37. The floating gates are formed like a self-matching state on the element separation ends of a channel widthwise direction and constituted of a plurality of polycrystal silicon films.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够浅控制通道轮廓的非挥发性半导体存储装置及其制造方法，提高杂质分布的可控性，以及进行元件的微细加工。解决方案：在外围电路中包括至少一个MOS晶体管的非易失性半导体存储器件设置有半导体衬底20，埋设在形成于半导体衬底20上的元件分离槽33中的元件隔离绝缘膜34，以形成多个元件形成区域，通过第一栅极绝缘膜25形成在各个元件形成区域中的浮动栅极26,29，通过第二栅极绝缘膜35形成在浮动栅极26,29上的控制栅极37以及源极 - 漏极区域 40通过与控制栅极37的自匹配形成在半导体衬底20上。浮动栅极在沟道宽度方向的元件分离端上形成为自匹配状态，并由多个多晶硅膜构成。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2004281663A Semiconductor memory device and its manufacturing method 审中-公开
公开(公告)号：JP2004281663A
公开(公告)日：2004-10-07
申请号：JP2003070140
申请日：2003-03-14
申请人： Toshiba Corp , 株式会社東芝
发明人： NARITA KAZUHITO , IIZUKA HIROHISA , HAZAMA HIROAKI
IPC分类号： H01L21/76 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To simultaneously process regions having different laminate structures in a gate structure of a semiconductor memory device.
SOLUTION: A method of manufacturing the semiconductor memory device comprises processes of forming a semiconductor layer 11, first insulation film 12, first electrode layer 13, element isolation region 15, and second insulation film 16 in order, all of which are common to a memory cell array region and a selector gate region; forming an opening 17 to expose a front surface of the first electrode layer 13 by removing the second insulation film 16 in the selector gate region; forming a second electrode layer 18 on top of the second insulation film 16 in the memory cell array region, and on the exposed surface of the first electrode layer 13 in the selector gate region; and forming a gate electrode of a memory transistor by removing the first electrode layer 13, the second insulation film 16, and the second electrode layer 18 by using the first insulation film 12 as a stopper in the memory cell array region in succession, as well as forming a gate electrode of a selector transistor by removing the first and second electrode layers 13 and 18 in the selector gate region in succession.
COPYRIGHT: (C)2005,JPO&NCIPI

4. 发明专利

JP2006313925A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2006313925A
公开(公告)日：2006-11-16
申请号：JP2006175635
申请日：2006-06-26
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA HIROSHI , ARITOME SEIICHI , IMAMIYA KENICHI , OHIRA HIDEKO , TAKEUCHI TAKESHI , SHIMIZU KAZUHIRO , NARITA KAZUHITO
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of preventing a failure caused by deterioration of etching accuracy in a region at a memory cell array end. SOLUTION: The semiconductor memory device includes first blocks 2-0, 2-N composed of first memory cell units to which a plurality of memory cells M 1 to M 8 are connected, and second blocks 2-1 to 2-(N-1) composed of second memory cell units to which a plurality of memory cells M 1 to M 8 are connected. A memory cell array 2 is constituted by disposing the first block at opposite ends and the second block at other portions. Constitution of the first memory cell unit on the side of the memory cell array end is different from that of the second memory cell unit. It is possible to prevent a failure caused by deterioration of etching accuracy of the region at the memory cell array end, and to realize high yield operation and high reliability operation substantially without causing an increase of a chip size. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止由存储单元阵列端的区域中的蚀刻精度劣化引起的故障的半导体存储器件。解决方案：半导体存储器件包括由第一存储单元单元组成的第一块2-0，2-N，多个存储单元M 1 至M SB 8 >与第二存储单元组合的第二块2-1至2-（N-1），多个存储单元M SB1至SBB < 被连接。存储单元阵列2通过将第一块布置在相对端部而将第二块布置在其它部分而构成。存储单元阵列端侧的第一存储单元单元的结构与第二存储单元单元的结构不同。可以防止由于存储单元阵列端的区域的蚀刻精度的劣化而导致的故障，并且实质上不会导致芯片尺寸的增加而实现高产量操作和高可靠性操作。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2005327792A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005327792A
公开(公告)日：2005-11-24
申请号：JP2004142306
申请日：2004-05-12
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMIYA EIJI , IIZUKA HIROHISA , HAZAMA HIROAKI , OTANI NORIO , NARITA KAZUHITO
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/04 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76897 , H01L21/26586 , H01L21/76802 , H01L21/76834 , H01L27/10873 , H01L27/10894
摘要： PROBLEM TO BE SOLVED: To reduce the number of photolithographic processes by integrating an ion implantation process and an oxide film removing process.
SOLUTION: After processing gate electrodes 7 of a memory cell region 1 and the gate electrode 8 of a high breakdown voltage transistor 3, only a portion between the gate electrodes 7 of selector gate transistors is opened by a resist pattern. An ion-implanted layer 4a for adjusting a threshold is formed below the gate electrodes 7, and then an oxide film 14 is separated. Thereafter, a nitride film 15 and a BPSG film 16 are buried and planarized, and then an oxide film 17 is formed. In a photolithographic process for forming contact holes 18 and 19; the oxide film 17 and the BPSG film 16 are etched, the nitride film 15 is etched, and the oxide film 14 is etched with different selectivity which can reduce the number of the photolithographic processes without giving damages.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过集成离子注入工艺和氧化膜去除工艺来减少光刻工艺的数量。解决方案：在处理存储单元区域1的栅电极7和高击穿电压晶体管3的栅电极8之后，只有选择栅极晶体管的栅电极7之间的部分被抗蚀剂图案打开。在栅电极7的下方形成用于调整阈值的离子注入层4a，然后分离氧化膜14。此后，将氮化物膜15和BPSG膜16埋入并平坦化，然后形成氧化物膜17。在用于形成接触孔18和19的光刻工艺中; 蚀刻氧化膜17和BPSG膜16，蚀刻氮化物膜15，并以不同的选择性蚀刻氧化物膜14，这可以减少光刻工艺的数量而不造成损害。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2003037194A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003037194A
公开(公告)日：2003-02-07
申请号：JP2001225071
申请日：2001-07-25
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MIYAWAKI SATOSHI , NARUGE KIYOMI , NARITA KAZUHITO , SAKAGAMI SHIGETO
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/768 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To manufacture a memory cell and a transistor(Tr) of the peripheral circuit of the memory cell in parallel without forming an MOS structure on the surface opposed to an element separation region 107 in the element region of the Tr, with no increase in the pattern area of the Tr.
SOLUTION: A tunnel oxide film, a first gate electrode material, and a first CMP stopper material are sequentially formed in the cell region on a silicon substrate. Then, a gate oxide film, a second gate electrode material, and a second CMP stopper material are sequentially formed in the peripheral circuit region on the silicon substrate. AN element region and an element separation region are formed in self-aligned manner on the substrate. An insulating film is formed on the surface of the first gate electrode material in the cell region, and a third gate electrode material is deposited on the surface of the insulating film.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了在与Tr的元件区域中与元件分离区域107相对的表面上并行地形成存储单元的外围电路的存储单元和晶体管（Tr）而不形成MOS结构， Tr的图案区域不增加。解决方案：在硅衬底上的单元区域中依次形成隧道氧化膜，第一栅极电极材料和第一CMP阻挡材料。然后，在硅衬底上的外围电路区域中依次形成栅极氧化膜，第二栅电极材料和第二CMP阻挡材料。在衬底上以自对准的方式形成AN元件区域和元件分离区域。在单元区域中的第一栅电极材料的表面上形成绝缘膜，并且在绝缘膜的表面上沉积第三栅电极材料。

7. 发明专利

JP2004356428A Nonvolatile semiconductor memory device and method for manufacturing the same 审中-公开
公开(公告)号：JP2004356428A
公开(公告)日：2004-12-16
申请号：JP2003152922
申请日：2003-05-29
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUCHI SUNAO , OTANI NORIO , TSUNODA HIROAKI , OKAJIMA MUTSUMI , NARITA KAZUHITO , IIZUKA HIROHISA , HAZAMA HIROAKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device with capacitance reduced between its floating gate electrodes, and to provide a method for manufacturing the same.
SOLUTION: A polycrystalline silicon film 200 is buried between memory cells in the word-line direction, the polycrystalline silicon film 200 is applied with a potential, and the nonvolatile semiconductor memory device thus constructed is used. In this memory device, capacitance between floating gate electrodes FG is lowered for a reduction in capacitance between memory cells, and this reduces mutual interference between the memory cells.
COPYRIGHT: (C)2005,JPO&NCIPI

8. 发明专利

JPH10326880A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10326880A
公开(公告)日：1998-12-08
申请号：JP13378097
申请日：1997-05-23
申请人： TOSHIBA CORP
发明人： SONODA MASAHISA , KAI NAOKI , TSUNODA HIROAKI , ARAKI HITOSHI , NARITA KAZUHITO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To improve uniformity of each element by preventing variability of the width of an element formation region and that of an element separation region. SOLUTION: In a method for manufacturing a semiconductor device, which contains a process for forming a silicon oxide film 22 on a semiconductor substrate 21, a process for forming a silicon film 23 on the silicon oxide film 22, a process for forming a silicon nitride film 24 on the silicon film 23, a process for selectively removing the silicon nitride film 24, and a process for heating the semiconductor substrate, in which the silicon nitride film 24 is selectively removed in an oxidizing atmosphere to form a field oxide film, a native oxide film of an interface between the silicon film 23 and the silicon nitride film 24 is suppressed to be a film of thickness 0.8 nm or less.

9. 发明专利

JPH10270575A NON-VOLATILE SEMICONDUCTOR MEMORY STORAGE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH10270575A
公开(公告)日：1998-10-09
申请号：JP6870297
申请日：1997-03-21
申请人： TOSHIBA CORP
发明人： SHIMIZU KAZUHIRO , NARITA KAZUHITO , ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory storage which generates no thinning of film on the surface of an element isolation region, and to provide the manufacturing method of the above-mentioned memory storage. SOLUTION: This semiconductor memory storage has a plurality of element isolation regions 112 which are formed on a silicon substrate 100 and used to divide a semiconductor active region 102, a source region 110S and a drain region 110D formed on the semiconductor active region 102 which is pinched by the element isolation region 112, a floating gate 106 which is capacitive coupled to the semiconductor active region 102 located between the source region 1105 and the drain region 110D, and a control gate 108 which is capacitive coupled to the floating gate 106 through the second gate insulating film 107. In this case, the second gate insulating film 107 is left on the area ranging from the upper surface of the element isolation region 112 under the control gate 108 to the upper surface of the element isolation region 112 other than the part under the control gate 108.

10. 发明专利

JPS6398131A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6398131A
公开(公告)日：1988-04-28
申请号：JP24457986
申请日：1986-10-15
申请人： TOSHIBA CORP
发明人： NARITA KAZUHITO , MORITA SHIGERU
IPC分类号： H01L21/316 , H01L21/76
摘要： PURPOSE:To narrow an element isolation region thereby to flatten an element isolation shape by selectively oxidizing a semiconductor substrate with a second antioxidative film as a mask and growing the remaining field oxide film to form an element isolation insulating film. CONSTITUTION:A surface protective film 12 is formed on a semiconductor substrate 11, a first antioxidative film 13 is formed on the film 12, and the film 13 is then selectively removed. Then, with the remaining film 13 as a mask the substrate 11 is selectively oxidized to form a field oxide film 14, all the film 13 is removed, the whole film 12 is removed by etching, and the film 14 partially remains. Then, a second antioxidative film 15 is formed on the exposed substrate 11, and it is selectively oxidized with the film 15 as a mask. Thereafter, the film 15 is all removed, and an element isolation insulating film 16 is formed. Thus, the width of the insulating film can be narrowed, and the element isolation shape can be flattened.

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