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1. 发明专利

JP2003007870A Non-volatile semiconductor memory and manufacturing t method therefor 有权
标题翻译：非挥发性半导体存储器及其制造方法
公开(公告)号：JP2003007870A
公开(公告)日：2003-01-10
申请号：JP2001193518
申请日：2001-06-26
申请人： Toshiba Corp , 株式会社東芝
发明人： ARITOME SEIICHI
IPC分类号： H01L21/3205 , H01L21/76 , H01L21/762 , H01L21/8247 , H01L23/52 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/115 , H01L27/11529 , H01L27/11543
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory having a structure which relaxes the difficulty in reducing the resistance of wiring which accompanies micronization of the non-volatile semiconductor memory.
SOLUTION: The non-volatile semiconductor memory comprises a memory cell transistor of stack gate type. The control gate of the memory cell transistor comprises a metal 29 embedded in a groove 25.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种非易失性半导体存储器，该非易失性半导体存储器具有放松难以减少伴随非易失性半导体存储器的微粉化的布线电阻的结构。解决方案：非易失性半导体存储器包括堆叠门型存储单元晶体管。存储单元晶体管的控制栅极包括嵌入槽25中的金属29。

2. 发明专利

JP2007300136A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2007300136A
公开(公告)日：2007-11-15
申请号：JP2007186274
申请日：2007-07-17
申请人： Toshiba Corp , 株式会社東芝
发明人： WATABE HIROSHI , YAEGASHI TOSHITAKE , ARITOME SEIICHI , SHIMIZU KAZUHIRO , TAKEUCHI YUJI
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce the resistance of a select gate electrode in a NAND cell unit.
SOLUTION: In a nonvolatile semiconductor memory, each of a first and a second select gate electrodes SGD has a plurality of contact regions regularly arranged in a row direction, lies adjacent to a column direction by holding the diffusion layer or the source diffusion layer of a NAND cell unit, and extending to a row direction. The contact region of the first gate electrode and the contact region of the second select gate electrode are arranged as they are not face to each other. An interconnect wire SDL formed upper layer than the first select gate electrode is connected in the region of the first select gate electrode. The interconnect wire SDL is disposed on a memory cell in the NAND cell unit in the first select gate electrode side.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：降低NAND单元单元中的选择栅电极的电阻。解决方案：在非易失性半导体存储器中，第一和第二选择栅电极SGD中的每一个具有沿行方向规则排列的多个接触区域，通过保持扩散层或源极扩散位于与列方向相邻的位置 NAND单元单元的层，并且延伸到行方向。第一栅电极的接触区域和第二选择栅电极的接触区域彼此不相对地布置。与第一选择栅电极相比形成的上层的互连线SDL连接在第一选择栅电极的区域中。互连线SDL设置在第一选择栅电极侧的NAND单元单元中的存储单元上。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007081434A Non-volatile semiconductor storage device 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：JP2007081434A
公开(公告)日：2007-03-29
申请号：JP2006337208
申请日：2006-12-14
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU KAZUHIRO , ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a fine flash memory with high integration, superior in element isolation capability, and with small parasitic resistors and capacitances. SOLUTION: A NAND type flash EEPROM is formed on SOI substrate. An element region (active layer) has a lattice pattern, and a groove between the lattice patterns is embedded by an insulator. Elements of row direction are perfectly separated by the insulator. A silicon thin film in which memory cell is formed contains a minute amount of n-type impurity, and is located near an intrinsic semiconductor. A silicon thin film which is formed with a peripheral circuit and a selective gate transistor is p-type. A diffusion layer of memory cell and the selective gate transistor is n-type. A channel of each memory cell which constitutes NAND strings is configured at least two regions where threshold values are different. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供高集成度，元件隔离能力优异以及小的寄生电阻和电容的精细闪存。解决方案：在SOI衬底上形成NAND型快闪EEPROM。元件区域（有源层）具有格子图案，栅格图案之间的沟槽被绝缘体嵌入。行方向的元素被绝缘体完全分离。其中形成存储单元的硅薄膜含有微量的n型杂质，并且位于本征半导体附近。形成有外围电路和选择栅极晶体管的硅薄膜是p型的。存储单元的扩散层和选择栅极晶体管是n型。构成NAND串的每个存储单元的通道配置有至少两个阈值不同的区域。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2004095145A Flash memory system and error correcting method 有权
公开(公告)号：JP2004095145A
公开(公告)日：2004-03-25
申请号：JP2003203290
申请日：2003-07-29
申请人： Toshiba Corp , 株式会社東芝
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/42
摘要： PROBLEM TO BE SOLVED: To shorten the time needed for program verification and erase verification and to prevent the threshold voltage from changing excessively even in the case of performing rewrite and reerase. SOLUTION: A memory unit is controlled in order to change the data stored in the memory unit, it is detected whether there is an error in data read from the memory unit, and, when there is the error, the error is corrected. Control is performed in order to change the data for the memory unit, and the number of pieces of data considered to have failed in data change is subsequently measured. If the measured number of pieces of data considered to have failed in the change is not higher than the predetermined prescribed number that is correctable, data change is considered to be successful. COPYRIGHT: (C)2004,JPO

5. 发明专利

JP2006313925A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2006313925A
公开(公告)日：2006-11-16
申请号：JP2006175635
申请日：2006-06-26
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA HIROSHI , ARITOME SEIICHI , IMAMIYA KENICHI , OHIRA HIDEKO , TAKEUCHI TAKESHI , SHIMIZU KAZUHIRO , NARITA KAZUHITO
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of preventing a failure caused by deterioration of etching accuracy in a region at a memory cell array end. SOLUTION: The semiconductor memory device includes first blocks 2-0, 2-N composed of first memory cell units to which a plurality of memory cells M 1 to M 8 are connected, and second blocks 2-1 to 2-(N-1) composed of second memory cell units to which a plurality of memory cells M 1 to M 8 are connected. A memory cell array 2 is constituted by disposing the first block at opposite ends and the second block at other portions. Constitution of the first memory cell unit on the side of the memory cell array end is different from that of the second memory cell unit. It is possible to prevent a failure caused by deterioration of etching accuracy of the region at the memory cell array end, and to realize high yield operation and high reliability operation substantially without causing an increase of a chip size. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止由存储单元阵列端的区域中的蚀刻精度劣化引起的故障的半导体存储器件。解决方案：半导体存储器件包括由第一存储单元单元组成的第一块2-0，2-N，多个存储单元M 1 至M SB 8 >与第二存储单元组合的第二块2-1至2-（N-1），多个存储单元M SB1至SBB < 被连接。存储单元阵列2通过将第一块布置在相对端部而将第二块布置在其它部分而构成。存储单元阵列端侧的第一存储单元单元的结构与第二存储单元单元的结构不同。可以防止由于存储单元阵列端的区域的蚀刻精度的劣化而导致的故障，并且实质上不会导致芯片尺寸的增加而实现高产量操作和高可靠性操作。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006013538A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2006013538A
公开(公告)日：2006-01-12
申请号：JP2005229895
申请日：2005-08-08
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA HIROSHI , OHIRA HIDEKO , IMAMIYA KENICHI , TAKEUCHI TAKESHI , ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L21/76 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent incorrect readout resulting from capacity coupling between wirings. SOLUTION: In blocks BLOCKi-1, BLOCKi, selective gate lines SG1 (149) are located, respectively. A contact section X1 to a selective gate line SG1 (149) in a block BLOCKi-1 is provided in a shunt region QQ. A selective gate bypass line 21i-1 is located in a block BLOCKi adjoining the block BLOCKi-1, although it connects with the selective gate line SG1 (149) in the block BLOCKi-1. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由布线之间的电容耦合引起的错误读取。解决方案：在块BLOCKi-1，BLOCKi，分别位于选择栅极线SG1（149）。在分路区域QQ中设置有与块BLOCKi-1中的选择栅极线SG1（149）的接触部分X1。选择栅极旁路线21i-1位于与块BLOCKi-1相邻的块BLOCKi中，尽管它与块BLOCKi-1中的选择栅极线SG1（149）连接。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2004158193A Non-volatile semiconductor memory 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：JP2004158193A
公开(公告)日：2004-06-03
申请号：JP2004032104
申请日：2004-02-09
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKEUCHI TAKESHI , TANAKA TOMOHARU , ARITOME SEIICHI , SAKUI YASUSHI
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide an EEPROM which allows random access to be accelerated, as a result of the reduction in the floating of a source line by forming the source line into low resistance without increasing the chip area. SOLUTION: This memory comprises a memory cell section constituted by one cell or a plurality of non-volatile memory cells, a signal line to perform data transfer with the memory cell section, and a selective transistor located between the signal line and the memory cell section. In write-protected operation, writing non-selective voltage is applied to the signal line, and by applying selective gate voltage higher than the writing non-selective voltage to a gate of the selective transistor, the writing non-selective voltage is transferred to a channel of the memory cell section. Writing gate voltage is then applied to a control gate of the memory cell, and write-protected channel voltage boosted by capacity coupling between the channel and the control gate of the memory cell is generated. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了提供允许随机访问加速的EEPROM，由于通过在不增加芯片面积的情况下将源极线形成为低电阻而使源极线的浮置减少的结果。解决方案：该存储器包括由一个单元或多个非易失性存储单元构成的存储单元部分，与存储单元部分进行数据传输的信号线，以及位于信号线和存储单元部分。在写保护动作中，对信号线施加写入非选择电压，通过将高于写入非选择电压的选择栅极电压施加到选择晶体管的栅极，写入非选择电压被转移到存储单元部分的通道。然后将写入栅极电压施加到存储器单元的控制栅极，并且产生通过存储器单元的通道和控制栅极之间的电容耦合升压的写保护通道电压。版权所有（C）2004，JPO

8. 发明专利

JP2003347439A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2003347439A
公开(公告)日：2003-12-05
申请号：JP2003128039
申请日：2003-05-06
申请人： Toshiba Corp , 株式会社東芝
发明人： ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To realize high integration and high reliability by eliminating variation in the memory cell characteristics due to misalignment.
SOLUTION: In the semiconductor memory where a plurality of memory cells are formed while being arranged on a semiconductor substrate, an isolation trench is made at least in a part of the semiconductor substrate between respective memory cells, a part of the isolation trench is filled with an insulating film for isolation and the remainder of the isolation trench is filled with a conductive film, at least a part of the side face of the isolation trench filled with the conductive film is a part of the tunnel part of a memory cell transistor.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过消除由于未对准引起的存储单元特性的变化，实现高集成度和高可靠性。解决方案：在布置在半导体衬底上形成多个存储单元的半导体存储器中，在各个存储单元之间至少在半导体衬底的一部分上形成隔离沟槽，隔离沟槽的一部分填充有用于隔离的绝缘膜，并且隔离沟槽的其余部分填充有导电膜，填充有导电膜的隔离沟槽的侧面的至少一部分是存储单元的隧道部分的一部分晶体管。版权所有（C）2004，JPO

9. 发明专利

JP2009272648A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2009272648A
公开(公告)日：2009-11-19
申请号：JP2009187679
申请日：2009-08-13
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA HIROSHI , OHIRA HIDEKO , IMAMIYA KENICHI , TAKEUCHI TAKESHI , ARITOME SEIICHI
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/06 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent incorrect readout due to capacitance coupling between wires. SOLUTION: Selective gate wires SG1 (149) are disposed in blocks BLOCKi-1 and BLOCKi, respectively. A contact portion X1 for the selective gate wire SG1 (149) in the block BLOCKi-1 is formed in a shunt area QQ. A selective gate bypass wire 21i-1, which is connected to the selective gate wire SG1 (149) in the block BLOCKi-1, is disposed in the block BLOCKi adjacent to the block BLOCKi-1. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：防止由于电线之间的电容耦合导致的错误读取。解决方案：选择栅极线SG1（149）分别设置在块BLOCKi-1和BLOCKi中。块BLOCKi-1中的选择栅极线SG1（149）的接触部分X1形成在分流区域QQ中。与块BLOCKi-1中的选择栅极线SG1（149）连接的选择栅极旁路布线21i-1被布置在与块BLOCKi-1相邻的块BLOCKi中。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2008235936A Non-volatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2008235936A
公开(公告)日：2008-10-02
申请号：JP2008137247
申请日：2008-05-26
申请人： Toshiba Corp , 株式会社東芝
发明人： YAEGASHI TOSHITAKE , SHIMIZU KAZUHIRO , ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device and a method of manufacturing the same, both of which are capable of reducing the number of manufacturing processes and has high-speed operability and high reliability.
SOLUTION: The non-volatile semiconductor memory device includes a memory cell, having a self-aligned two-layer gate structure which includes a gate insulating film formed on a semiconductor substrate, a first conductor 3 serving as a floating gate layer, a second conductor 7 serving as a control gate layer, and an insulation film 6 for electrically insulating the first conductor and the second conductor. The memory cell unit is constituted by connecting a plurality of the memory cells in series. A gate transistor is connected to the memory cell unit in series. A resistance element is constituted, by using the two-layer gate structure, the first conductor is used as a resistor, and the second conductor and the insulation film are removed, with respect to a region of a part of the first conductor.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了提供一种非易失性半导体存储器件及其制造方法，它们都能够减少制造工艺的数量并且具有高速可操作性和高可靠性。解决方案：非易失性半导体存储器件包括具有自对准双层栅极结构的存储单元，其包括形成在半导体衬底上的栅绝缘膜，用作浮栅的第一导体3，用作控制栅极层的第二导体7和用于使第一导体和第二导体电绝缘的绝缘膜6。存储单元单元通过串联连接多个存储单元来构成。栅极晶体管串联连接到存储单元单元。电阻元件通过使用双层栅极结构，第一导体用作电阻器，并且第二导体和绝缘膜相对于第一导体的一部分的区域被去除。版权所有（C）2009，JPO＆INPIT

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