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1. 发明专利

JP2006269554A Nonvolatile semiconductor memory device and its manufacturing method 审中-公开
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：JP2006269554A
公开(公告)日：2006-10-05
申请号：JP2005082605
申请日：2005-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAKI HITOSHI
IPC分类号： H01L21/8247 , H01L21/76 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which cancels an insulation fault in the nonvolatile semiconductor memory device which carried out isolation formation with an STI technology, and to provide a method of manufacturing it.
SOLUTION: A second polysilicon layer 109 which serves as a floating gate electrode with first polysilicon layer 103 is formed on the element isolation region 108 of the first polysilicon layer 103 and the STI structure. A second gate insulating film 111 is formed on the second polysilicon layer 109 and the floating gate electrode isolation region 110. The third polysilicon layer 112 and the first metal silicide layer 113 used as a control gate electrode are formed on the second gate insulating film 111. The floating gate electrode 115 and the control gate electrode 116 are formed by etching so that these multilayer films may go direct with the element isolation region 108. The element isolation region 108 is formed so that the flattened surface of the element isolation regions other than both electrode formation region is lower than the semiconductor substrate 101.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种消除用STI技术进行隔离形成的非易失性半导体存储器件中的绝缘故障的非易失性半导体存储器件，并提供其制造方法。解决方案：在第一多晶硅层103的元件隔离区域108和STI结构上形成用作具有第一多晶硅层103的浮栅的第二多晶硅层109。第二栅极绝缘膜111形成在第二多晶硅层109和浮栅电极隔离区域110上。用作控制栅电极的第三多晶硅层112和第一金属硅化物层113形成在第二栅极绝缘膜111上通过蚀刻形成浮栅电极115和控制栅电极116，使得这些多层膜可以与元件隔离区域108直接连接。元件隔离区域108形成为使得元件隔离区域的平坦化表面不是电极形成区域都比半导体衬底101低。（C）2007，JPO＆INPIT

2. 发明专利

JPH0878551A NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION THEREOF 失效
公开(公告)号：JPH0878551A
公开(公告)日：1996-03-22
申请号：JP27747094
申请日：1994-11-11
申请人： TOSHIBA CORP
发明人： ARAKI HITOSHI
IPC分类号： G11C17/00 , G11C16/04 , G11C16/08 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/02 , G11C16/06
摘要： PURPOSE: To achieve high integration by realizing a select transistor in which the number of contact holes is decreased by eliminating the need of opening a contact hole in a first high resistance polysilicon. CONSTITUTION: The nonvolatile semiconductor memory comprises a select transistor 209 having a floating gate similar to that of a multilayer memory cell 208. Since no contact hole is opened through a first high resistance polysilicon 204, the gate wiring of the select transilstor requires no contact hole to be opened in the way of a cell array. The floating gate 204 is precharged so that the select transistor 209 has a positive threshold or impurities are introduced into the channel region of the select transistor 209 while being controlled to have a positive neutral threshold by UV irradiation.

3. 发明专利

JPH0563208A NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0563208A
公开(公告)日：1993-03-12
申请号：JP1239892
申请日：1992-01-27
申请人： TOSHIBA CORP
发明人： ARAKI HITOSHI , SASAKI HIROYUKI , KANEBAKO KAZUNORI
IPC分类号： H01L21/316 , H01L21/314 , H01L21/318 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide a nonvolatile semiconductor memory having higher reliability concerning its charge holding characteristic and its manufacturing method. CONSTITUTION:A memory cell 100 is formed in the main surface region of a semiconductor board 10. An insulating film 26 between layers is formed on the board 10 so as to cover the memory cell 10. And a hole 28 is formed in the insulating film 26 up to the memory cell 100. an internal wiring layer 30 is electrically connected to the memory cell 100 through the hole 28. A protective film 32 is formed on the insulating film 26 so as to cover the internal wiring layer 30. And the protective film 32 is made out of material containing at least silicon and oxygen, and its refractive index is set in a range of 1.48 to 1.65. In this way, the protective film has a high screening effect on moving ions, water, etc., and makes it possible to increase the charge holding characteristic of the memory.

4. 发明专利

JPH0329369A ULTRAVIOLET RAYS ERASURE TYPE NON-VOLATILE SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT HAVING A PLURALITY OF DEVICES 失效
公开(公告)号：JPH0329369A
公开(公告)日：1991-02-07
申请号：JP16319889
申请日：1989-06-26
申请人： TOSHIBA CORP
发明人： ARAKI HITOSHI
IPC分类号： H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent memory erasure characteristics from being deteriorated by enabling one side surface which exists along the channel width direction of a wiring layer to be present on an extended line in vertical direction for a semiconductor substrate in the other side surface along the channel width direction of a first gate electrode or on the first gate electrode. CONSTITUTION:Even if a wiring layer 113 which is formed nearly in parallel to control gates 107a and 107b existing on the upper part of floating gates 105a and 105b and are formed being extended in the channel width direction exists, one side surface existing along the channel width direction of this wiring layer 113 exists on an extended line to the vertical direction for a semiconductor substrate 101 of the other side surface along the channel width direction of the floating gates 105a and 105b or on the floating gates 105a and 105b. Thus, ultraviolet rays are constantly irradiated onto the side surface existing along the channel width direction of the floating gates 105a and 105b, thus preventing memory erasure characteristics from being deteriorated even a multilayer wiring structure is applied to.

5. 发明专利

JPH09289209A INSULATION FILM USED FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09289209A
公开(公告)日：1997-11-04
申请号：JP10097796
申请日：1996-04-23
申请人： TOSHIBA CORP
发明人： SONODA MASAHISA , SHUDO SUSUMU , TANAKA MIWA , ARAKI HITOSHI , IDAKA TOSHIAKI , TSUNODA HIROAKI
IPC分类号： H01L21/8247 , H01L21/316 , H01L21/318 , H01L21/768 , H01L21/8242 , H01L23/00 , H01L23/29 , H01L23/522 , H01L23/532 , H01L27/108 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent electron trapping and improve moisture resistance. SOLUTION: When a CVD film (interlayer insulation film or passivation film) is manufactured using stock gas containing gas having an Si-H bond, production of electron trapping in a gate oxide film or a tunnel oxide film is suppressed by setting the amount of the Si-H bond in the CVD film to 0.6×10 cm or less, and hence a threshold of a transistor is prevented from being varied. Further, moisture resistance is improved by the refractive index of the CVD film to 1.65 or more or nitrogen concentration in the CVD film to 3×10 cm or more.

6. 发明专利

JPH09260553A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREFOR 失效
公开(公告)号：JPH09260553A
公开(公告)日：1997-10-03
申请号：JP7218396
申请日：1996-03-27
申请人： TOSHIBA CORP
发明人： ARAKI HITOSHI
IPC分类号： H01L23/29 , H01L21/822 , H01L23/31 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To effectively prevent diffusion of charged particles and to suppress improper products caused by the charged particles by forming a floating electrode on a semiconductor substrate near a pad electrode through an insulating film and by providing a means which infuses electric charges into the floating electrode. SOLUTION: A floating electrode 5 is formed on a semiconductor substrate 1 between a pad electrode 12 and a transistor through a first insulating film 4. A controlling gate electrode 7 is formed on the floating electrode 5 through a second insulating film 6. A positive voltage for example about 20V comparing to a potential of the semiconductor substrate 1 is impressed to the gate electrode 7 and a potential of the floating electrode 6 is elevated by coupling through the insulating film 6. By the means electrons is infused into the floating electrode 5 by FN tunnel current being flowed through the first gate oxide film 4 by the voltage between the floating electrode 5 and the semiconductor substrate 1. Also holes can be infused into the floating electrode 5 by impressing a negative high voltage to the controlling gate 7.

7. 发明专利

JPH0982926A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0982926A
公开(公告)日：1997-03-28
申请号：JP23991695
申请日：1995-09-19
申请人： TOSHIBA CORP
发明人： ABE MACHIKO , ARAKI HITOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To enable reduction in the width of a memory cell array by making a pitch between bit lines very fine, in a semiconductor storage device having a plurality of memory cells. SOLUTION: A semiconductor storage device is provided with a plurality of MOS transistors constituting memory cells, and a word line 108 which intersects channel regions of the MOS transistors, in a memory cell array. Two drain diffusion layers 102a-102d turning to the respective drain regions of the two MOS transistors and one source diffusion layer 103a, 103b turning to source regions of the two MOS transistors are alternately arranged interposing the word line 108. The source diffusion layers 103a, 103b are mutually connected through a source line 118.

8. 发明专利

JPH08316438A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH08316438A
公开(公告)日：1996-11-29
申请号：JP11544095
申请日：1995-05-15
申请人： TOSHIBA CORP
发明人： ARAKI HITOSHI
IPC分类号： H01L21/8247 , H01L27/115
摘要： PURPOSE: To prevent threshold rise of '1' cell and data inversion in long time read by installing a tunnel oxide film for write/erase and a read-only oxide film in a memory cell. CONSTITUTION: A plurality of memory cells controlled by control gate electrodes CG1-CG8 are connected in series. Selection transistors SGd, SGs are arranged on the series connection end portions, i.e., the drain D side and the source S side. The memory cells connected in series are arranged in parallel, and floating gates under common control gates are made common. One series connection memory cell group out of NAND type memory cells connected in parallel is formed of a tunnel oxide film in order to be operated exclusively for write/ erase. The other series connection memory cell group is formed of a read oxide film, in order to be operated exclusively for read. The tunnel oxide film is an oxide film thinner than the read oxide film.

9. 发明专利

JPH06350093A MANUFACTURE OF NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06350093A
公开(公告)日：1994-12-22
申请号：JP13458493
申请日：1993-06-04
申请人： TOSHIBA CORP
发明人： ARAKI HITOSHI
IPC分类号： H01L21/8247 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide a method of manufacturing a nonvolatile semiconductor memory which forms an oxide film enabling the charge holding characteristic to be improved on the sides of a floating gate. CONSTITUTION:A silicon oxide 16 covering over a silicon substrate 10, which contains the top and sides of a control gate electrode 14 and the sides of a suspended gate electrode 13, is formed by thermal oxidation or chemical vapor phase epitaxy. And it is subjected to rapid nitriding within 60 seconds by infrared lamp heating in an NH3 atmosphere over a substrate temperature range of 800 deg. to 1100 deg.C to convert a silicon oxide 16 to silicon nitride oxide 16'.

10. 发明专利

JP2005050419A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2005050419A
公开(公告)日：2005-02-24
申请号：JP2003204751
申请日：2003-07-31
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAKI HITOSHI
IPC分类号： G11C16/04 , G11C16/02 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which improves rewriting reliability of information and electrically performs rewriting of the information. SOLUTION: The nonvolatile semiconductor storage device is equipped with a first information writing region 13a, second information writing region 13b, first management information writing region 14a and second management information writing region 14b, where memory cell arrays 12x and 12y provided with a plurality of transistors 19x and 19y for storage to permit electrical rewriting of the information are respectively arranged. The transistors 19y disposed in both the management information writing regions 14a and 14b are greater in the size of at least either of their gate length Ly or gate width Wy than the size of the gate length Lx or gate width Wx of the transistors 19x for storage disposed in both the information writing regions14a and 14b. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种提高信息的重写可靠性并电气地执行信息重写的非易失性半导体存储装置。解决方案：非易失性半导体存储装置配备有第一信息写入区域13a，第二信息写入区域13b，第一管理信息写入区域14a和第二管理信息写入区域14b，其中存储单元阵列12x和12y设置有分别布置用于存储以允许电气重写信息的多个晶体管19x和19y。设置在管理信息写入区域14a和14b两者中的晶体管19y的栅极长度Ly或栅极宽度Wy中的至少一个的尺寸大于栅极长度Lx或栅极宽度Wx的尺寸，晶体管19x用于存储设置在信息写入区域14a和14b中。版权所有（C）2005，JPO＆NCIPI

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