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1. 发明专利

JP2010211922A Sense amplifier circuit 有权
标题翻译：感应放大器电路
公开(公告)号：JP2010211922A
公开(公告)日：2010-09-24
申请号：JP2010138331
申请日：2010-06-17
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , MATSUDA HIROYUKI , HONDA YASUHIKO , KATO HIDEO
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To enable high-speed reading by shortening an overcharge period. SOLUTION: The sense amplifier circuit includes: a current mirror circuit 1; a precharge circuit 2 and a load circuit 3 having output parts connected to the input part of the input circuit side of the current mirror circuit 1; and a precharge circuit 2R and a load circuit 3R having output parts connected to the input part of the comparison circuit side of the current mirror circuit 1. Counter capacitors 8 and 8R are disposed for canceling gate coupling of Pch transistors PTR2a and PRT2Ra constituting the precharge circuits 2 and 2R. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过缩短过充电期间来实现高速读取。解决方案：读出放大器电路包括：电流镜电路1; 预充电电路2和负载电路3，其输出部分连接到电流镜电路1的输入电路侧的输入部分; 以及预充电电路2R和负载电路3R，其输出部分连接到电流镜电路1的比较电路侧的输入部分。计数器电容器8和8R被设置用于抵消构成预充电的Pch晶体管PTR2a和PRT2Ra的栅极耦合电路2和2R。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2006101626A Four-phase clock driven charge pump circuit 有权
标题翻译：四相时钟驱动充电泵电路
公开(公告)号：JP2006101626A
公开(公告)日：2006-04-13
申请号：JP2004284119
申请日：2004-09-29
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , CHIN GIYOUSHIYOU , MATOBA SHINJI , KURIYAMA MASAO , KATO HIDEO
IPC分类号： H02M3/07 , H03K17/06 , H03K17/687
摘要： PROBLEM TO BE SOLVED: To provide a four-phase clock driven charge pump circuit that can operate at a high speed and enhance the pump capability. SOLUTION: A pump circuit is provided, and has n-channel transistors T12-T1(n+1), capacitors C1-Cn connected to drains of the n-channel transistors T12-T1(n+1) at one end, n-channel transistors T32-T3(n+1) having gates and drains mutually connected and also connected to one end of the capacitors C1-Cn, and having sources connected to gates of the n-channel transistors T12-T1(n+1), and capacitors Cm2-Cm(n+1) connected to the gates of the n-channel transistors T12-T1(n+1) at one end. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以高速运行并提高泵功能的四相时钟驱动电荷泵电路。解决方案：提供泵电路，并且具有n沟道晶体管T12-T1（n + 1），在一端连接到n沟道晶体管T12-T1（n + 1）的漏极的电容器C1-Cn 具有相互连接并且也连接到电容器C1-Cn的一端的栅极和漏极的n沟道晶体管T32-T3（n + 1），并且具有连接到n沟道晶体管T12-T1（n + 以及在一端连接到n沟道晶体管T12-T1（n + 1）的栅极的电容器Cm2-Cm（n + 1）。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2010207092A Four-phase clock driven charge pump circuit 有权
标题翻译：四相时钟驱动充电泵电路
公开(公告)号：JP2010207092A
公开(公告)日：2010-09-16
申请号：JP2010141023
申请日：2010-06-21
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , CHIN GYOSHO , MATOBA SHINJI , KURIYAMA MASAO , KATO HIDEO
IPC分类号： H02M3/07
摘要： PROBLEM TO BE SOLVED: To avoid breakdown of elements caused by application of a high voltage.
SOLUTION: A four-phase clock driven charge pump circuit includes capacitors C1-C(n-3), Cp1-Cp3 with one end of them to be connected, respectively, to the connective points of Nch transistors T1-T(n+1) connected in series and capacitors Cs1-Csn, Cq with one end of them to be connected, respectively, to the gates of Nch transistors T1-T(n+1). The voltage having an amplitude equal to the amplitude Vcc of a clock signal obtained through the use of a quadruple booster circuit after quadruplicating the amplitude Vcc is supplied to the other end of the capacitors C1-C(n-3). The voltage having an amplitude equal to the amplitude Vcc obtained through the use of a double booster circuit after doubling the amplitude Vcc is supplied to the other end of the capacitor Cp. The voltage having an amplitude equal to the amplitude Vcc obtained through the use of the quadruple booster circuit after quadruplicating the amplitude Vcc is supplied to the other end of the capacitors Cs1-Cs(n-3). The voltage having an amplitude equal to the amplitude Vcc obtained through the use of the quadruple booster circuit after quadruplicating the amplitude Vcc is supplied to the other end of the capacitor Cq.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：避免因应用高电压引起的元件故障。解决方案：四相时钟驱动电荷泵电路包括分别连接到Nch晶体管T1-T（n-3）的连接点的电容器C1-C（n-3），Cp1-Cp3， n + 1）和电容器Cs1-Csn，Cq分别与Nch晶体管T1-T（n + 1）的栅极连接。电容器C1-C（n-3）的另一端具有等于通过使用四次升压电路而获得的时钟信号的振幅Vcc的电压。具有等于振幅Vcc加倍后通过使用双升压电路获得的振幅Vcc的电压被提供给电容器Cp的另一端。振幅等于振幅Vcc一式四份后通过使用四极升压电路获得的振幅Vcc的电压被提供给电容器Cs1-Cs（n-3）的另一端。具有等于振幅Vcc一倍大的通过使用四极升压电路获得的振幅Vcc的电压被提供给电容器Cq的另一端。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2007164842A Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：JP2007164842A
公开(公告)日：2007-06-28
申请号：JP2005356532
申请日：2005-12-09
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： HIRANO MAKOTO , ASANO MASAMICHI , KATO HIDEO , SAITO SAKATOSHI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory capable of reducing the chip area of a reference side, and performing high-speed reading. SOLUTION: A signal EQ is started simultaneously with a precharging start. Thus, transistors 201 to 328 and R201 to 232 are turned ON, and data lines HON1 to HON128 and reference lines REF1 to REF32 are quickly charged by a precharge circuit 401 via a common line COM. As the data lines and the reference lines are connected in common via the transistors 201 to 328 and R201 to R232 to be equalized, the data lines and the reference lines are uniformly charged. As the data lines and the reference lines are uniformly charged at a high speed, high-speed reading is carried out within a short time. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够减小参考侧的芯片面积并进行高速读取的非易失性存储器。
解决方案：信号EQ与预充电开始同时启动。因此，晶体管201至328和R201至232导通，并且数据线HON1至HON128和参考线REF1至REF32由预充电电路401经由公共线COM快速充电。由于数据线和参考线通过晶体管201至328和R201至R232共同连接以进行均衡，因此数据线和参考线均匀充电。由于数据线和参考线以高速均匀充电，所以在短时间内进行高速读取。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006101627A Two-phase clock driven charge pump circuit, four-phase clock driven charge pump circuit, and voltage boosting circuit 有权
标题翻译：两相时钟驱动充电泵电路，四相时钟驱动充电泵电路和电压升压电路
公开(公告)号：JP2006101627A
公开(公告)日：2006-04-13
申请号：JP2004284120
申请日：2004-09-29
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , CHIN GIYOUSHIYOU , MATOBA SHINJI , KURIYAMA MASAO , KATO HIDEO
IPC分类号： H02M3/07 , H03K17/06 , H03K17/08 , H03K17/687 , H03K19/094
摘要： PROBLEM TO BE SOLVED: To avoid damages to an element due to the application of a high voltage. SOLUTION: A charge pump circuit has n-channel transistors T1-T(n+1) connected in series, and capacitors C1-C(n-1), Cp. The other end of the capacitors C1-C(n-1) other than a last stage is supplied with a voltage, whose amplitude is 2×Vcc level acquired by multiplying the amplitude Vcc of a clock signal by 2, using voltage doubler circuits A1-A(n-1). The other end of the capacitor Cp in the last stage is supplied with the clock signal CLK whose amplitude is of Vcc level. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：避免因施加高电压而损坏元件。解决方案：电荷泵电路具有串联连接的n沟道晶体管T1-T（n + 1）和电容器C1-C（n-1），Cp。电容器C1-C（n-1）的另一端不是最后一级被提供一个电压，其振幅是通过将时钟信号的振幅Vcc乘以2获得的2×Vcc电平，使用倍压器电路A1 -A（N-1）。在最后级的电容器Cp的另一端提供振幅为Vcc电平的时钟信号CLK。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2006099862A Sense amplifier circuit 有权
标题翻译：感应放大器电路
公开(公告)号：JP2006099862A
公开(公告)日：2006-04-13
申请号：JP2004284121
申请日：2004-09-29
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , MATSUDA HIROYUKI , HONDA YASUHIKO , KATO HIDEO
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To perform high-speed reading by shortening the period of overcharging. SOLUTION: This sense amplifier circuit comprises a current mirror circuit 1, a precharge circuit 2, and a load circuit 3 whose output parts are connected to the input part of the input circuit side of the current mirror circuit 1, a precharge circuit 2R and a load circuit 3R whose output parts are connected to the input part of the comparator circuit side of the current mirror circuit 1. Counter capacitor circuits 8 and 8R are provided to cancel the gate coupling of Pch transistors PTR2a and PRT2Rb constituting the precharge circuits 2 and 2R. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过缩短过充电周期来执行高速读取。解决方案：该感测放大器电路包括电流镜电路1，预充电电路2和负载电路3，其输出部分连接到电流镜电路1的输入电路侧的输入部分，预充电电路 2R和负载电路3R，其输出部分连接到电流镜电路1的比较器电路侧的输入部分。提供反电容电路8和8R以消除构成预充电电路的Pch晶体管PTR2a和PRT2Rb的栅极耦合 2和2R。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2003068100A Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：JP2003068100A
公开(公告)日：2003-03-07
申请号：JP2002220047
申请日：2002-07-29
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAI HIROTO , KATO HIDEO , ASANO MASAMICHI , TOKUSHIGE KAORU , YAMAMURA TOSHIO
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C29/00 , G11C29/14 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To specify a write defective bit line. SOLUTION: A nonvolatile memory has a nonvolatile memory cell array, an address buffer for storing an address inputted from the outside, a decoder for selecting a plurality of memory cells from the memory cell array in accordance with the address stored in the address buffer, a data register to which data from the plurality of nonvolatile memory cell selected by the decoder is inputted and which outputs these inputted data, a plurality of external control signal input terminals, and data input/output terminals connected to the data register and the address buffer. A command input mode decided in accordance with the combination of a plurality of external control signals is allowed. When a register read-command is inputted to the input/output terminal in this command input mode, the contents of the address buffer are outputted to the input/ output terminal.
摘要翻译：要解决的问题：指定写入缺陷位线。解决方案：非易失性存储器具有非易失性存储单元阵列，用于存储从外部输入的地址的地址缓冲器，用于根据存储在地址缓冲器中的地址从存储单元阵列中选择多个存储单元的解码器，输入由解码器选择的多个非易失性存储单元的数据并输出这些输入数据的数据寄存器，多个外部控制信号输入端和连接到数据寄存器和地址缓冲器的数据输入/输出端。允许根据多个外部控制信号的组合决定的命令输入模式。在该命令输入模式下，当向输入/输出端子输入寄存器读取命令时，将地址缓冲器的内容输出到输入/输出端子。

8. 发明专利

JP2004095168A Nonvolatile semiconductor storage device, cache memory system, semiconductor storage device and semiconductor storage system 有权
公开(公告)号：JP2004095168A
公开(公告)日：2004-03-25
申请号：JP2003338529
申请日：2003-09-29
申请人： Toshiba Corp , 株式会社東芝
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C29/00 , G11C29/42 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To shorten the time needed for program verification and erasure verification and also to prevent the threshold voltage from changing too much even if rewriting and reerasing are performed. SOLUTION: This nonvolatile semiconductor storage device is provided with a plurality of electrically rewritable nonvolatile semiconductor memory cells, a word line connected to the plurality of memory cells in common, a source line connected to the plurality of memory cells in common, a row decoder for supplying the word line with write verification voltage, a plurality of bit lines connected to the corresponding bit lines respectively, and a plurality of write verifying circuits provided in the corresponding bit lines respectively. Each of the write verifying circuit stores data of a first or second logical level. The write verifying circuits charge a corresponding bit line in advance and detect a write state of the corresponding memory cells after a prescribed time in the case of storing the data of the first logical level. The write verifying circuits connect a corresponding bit line to a prescribed power supply at least for the prescribed time in the case of storing the data of the second logical level. COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2012084225A Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：JP2012084225A
公开(公告)日：2012-04-26
申请号：JP2012017177
申请日：2012-01-30
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： HIRANO MAKOTO , ASANO MASAMICHI , KATO HIDEO , SAITO SAKATOSHI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory capable of reducing a chip area in a reference side and performing a high-speed reading.SOLUTION: A signal EQ is started simultaneously with a precharging start. Thus, transistors 201-328 and R201-202 are turned on, and data lines HON1-HON128 and reference lines REF1-REF2 are quickly charged by a precharge circuit 401 via a common line COM. As the data lines and the reference lines are connected in common via the transistors 201-328 and R201-R202 to be equalized, the data lines and the reference lines are uniformly charged. As the data lines and the reference lines are uniformly charged at a high speed, high-speed reading can be performed within a short time.
摘要翻译：要解决的问题：提供一种能够减小参考侧的芯片面积并进行高速读取的非易失性存储器。
解决方案：信号EQ与预充电开始同时启动。因此，晶体管201-328和R201-202导通，并且数据线HON1-HON128和参考线REF1-REF2通过公共线COM被预充电电路401快速充电。由于数据线和参考线通过晶体管201-328和R201-R202共同连接以进行均衡，所以数据线和参考线均匀地充电。随着数据线和参考线被高速均匀充电，可以在短时间内执行高速读取。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2004095145A Flash memory system and error correcting method 有权
公开(公告)号：JP2004095145A
公开(公告)日：2004-03-25
申请号：JP2003203290
申请日：2003-07-29
申请人： Toshiba Corp , 株式会社東芝
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/42
摘要： PROBLEM TO BE SOLVED: To shorten the time needed for program verification and erase verification and to prevent the threshold voltage from changing excessively even in the case of performing rewrite and reerase. SOLUTION: A memory unit is controlled in order to change the data stored in the memory unit, it is detected whether there is an error in data read from the memory unit, and, when there is the error, the error is corrected. Control is performed in order to change the data for the memory unit, and the number of pieces of data considered to have failed in data change is subsequently measured. If the measured number of pieces of data considered to have failed in the change is not higher than the predetermined prescribed number that is correctable, data change is considered to be successful. COPYRIGHT: (C)2004,JPO

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