专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2008140501A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2008140501A
公开(公告)日：2008-06-19
申请号：JP2006326950
申请日：2006-12-04
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： KODA HIDE , SAITO SAKATOSHI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of reducing wiring for control when a plurality of semiconductor memories are used.
SOLUTION: An input buffer 11 receives a chip-enable signal from the outside and outputs signals CEIN to input buffers 13-m to 13-O, thus outputting addresses supplied to terminals A to A to a memory array via the buffers 13-m to 13-O, reading data from the memory array, and supplying the data to output buffers 17-n to 17-O. An input buffer 14 receives a chip selection address inputted to a terminal AD from the outside and compares it with an internal address, and outputs a chip selection signal CEIN2 when both agree. An input buffer 15 receives the chip selection signal CEIN2, and outputs an output instruction signal OEIN when receiving an output instruction from the outside. The output buffers 17-n to 17-O are enabled by receiving the output instruction signal OEIN and output data read from the memory array to data terminals D to D .
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种当使用多个半导体存储器时能够减少用于控制的布线的半导体存储器。
解决方案：输入缓冲器11从外部接收芯片使能信号并向输入缓冲器13-m-13-O输出信号CEIN，从而将提供给端子A 的地址输出到A < 存储器阵列经由缓冲器13-m至13-O，从存储器阵列读取数据，并将数据提供给输出缓冲器17-n至17-O。输入缓冲器14从外部接收输入到终端AD的芯片选择地址，并将其与内部地址进行比较，并且当两者一致时输出芯片选择信号CEIN2。输入缓冲器15接收芯片选择信号CEIN2，并在从外部接收输出指令时输出输出指令信号OEIN。输出缓冲器17-n至17-O通过接收输出指令信号OEIN和将从存储器阵列读取的数据输出到数据端子D n至D O而被使能。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2011108294A Device for testing semiconductor memory 有权
标题翻译：用于测试半导体存储器的器件
公开(公告)号：JP2011108294A
公开(公告)日：2011-06-02
申请号：JP2009258985
申请日：2009-11-12
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： HIROSHIMA MASAHITO , SAITO SAKATOSHI
IPC分类号： G11C29/56
摘要： PROBLEM TO BE SOLVED: To provide a device for testing a semiconductor memory, which determines the presence of separate bits without a long use of a testor. SOLUTION: The device for testing the semiconductor memory includes: a first determination unit which determines the presence of defective memory cells of the semiconductor memory which have separate bits on predetermined bit by bit basis; memory units which store the information on the memory cells determined as defective ones at the first determination unit; a counter which stores the number of the separate bits on the bit by bit basis in the memory and counts the number for determining the presence of defective memory cells on the bit by bit basis; and a second determination unit which determines the presence of defective memory cells based on the number of the separate bits counted by the counter. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供用于测试半导体存储器的装置，其确定不存在长时间使用测试器的单独位的存在。解决方案：用于测试半导体存储器的装置包括：第一确定单元，其基于预定的逐位确定具有分离位的半导体存储器的存储单元的存在; 存储单元，其存储在所述第一确定单元处被确定为有缺陷的存储器单元的信息; 在存储器中逐位存储单独位的数量的计数器，并逐位计数确定有缺陷存储单元的存在的数量; 以及第二确定单元，其基于由计数器计数的单独位的数量来确定存在缺陷存储器单元的情况。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2007164844A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2007164844A
公开(公告)日：2007-06-28
申请号：JP2005356534
申请日：2005-12-09
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： HIROSHIMA MASAHITO , SAITO SAKATOSHI
IPC分类号： G11C29/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a defective part can be replaced by a redundant cell when a defect is caused in a memory cell when a memory is used actually. SOLUTION: An information storing memory 9 is constituted of a first latch reading the memory cell and output of the memory cell, and a second latch reading output of the first latch. After writing in the memory cell, a control circuit 3 reads out written data with a lightly lower level than a write-in threshold value and writes it in the first latch, verification of write-in about data written in the first latch is performed, after verification of write-in, data of the memory cell is read out with lower read-out level than the verification level and written in the first latch, successively, data of the first latch is written in the second latch. Then, a defective block is replaced by a redundant block based on data in the second latch. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储器，其中当实际使用存储器时，当在存储单元中引起缺陷时，可以用冗余单元替换缺陷部分。解决方案：信息存储存储器9由读取存储单元的第一锁存器和存储单元的输出以及第一锁存器的第二锁存器读出输出构成。在存储单元中写入之后，控制电路3以低于写入阈值的低电平读出写入数据，并将其写入第一锁存器，执行写入第一锁存器中的数据的写入验证，在写入验证之后，以比验证电平更低的读出电平读出存储单元的数据并连续地写入第一锁存器中，将第一锁存器的数据写入第二锁存器。然后，基于第二锁存器中的数据，由冗余块替换有缺陷的块。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007164842A Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：JP2007164842A
公开(公告)日：2007-06-28
申请号：JP2005356532
申请日：2005-12-09
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： HIRANO MAKOTO , ASANO MASAMICHI , KATO HIDEO , SAITO SAKATOSHI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory capable of reducing the chip area of a reference side, and performing high-speed reading. SOLUTION: A signal EQ is started simultaneously with a precharging start. Thus, transistors 201 to 328 and R201 to 232 are turned ON, and data lines HON1 to HON128 and reference lines REF1 to REF32 are quickly charged by a precharge circuit 401 via a common line COM. As the data lines and the reference lines are connected in common via the transistors 201 to 328 and R201 to R232 to be equalized, the data lines and the reference lines are uniformly charged. As the data lines and the reference lines are uniformly charged at a high speed, high-speed reading is carried out within a short time. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够减小参考侧的芯片面积并进行高速读取的非易失性存储器。
解决方案：信号EQ与预充电开始同时启动。因此，晶体管201至328和R201至232导通，并且数据线HON1至HON128和参考线REF1至REF32由预充电电路401经由公共线COM快速充电。由于数据线和参考线通过晶体管201至328和R201至R232共同连接以进行均衡，因此数据线和参考线均匀充电。由于数据线和参考线以高速均匀充电，所以在短时间内进行高速读取。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2012084225A Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：JP2012084225A
公开(公告)日：2012-04-26
申请号：JP2012017177
申请日：2012-01-30
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： HIRANO MAKOTO , ASANO MASAMICHI , KATO HIDEO , SAITO SAKATOSHI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory capable of reducing a chip area in a reference side and performing a high-speed reading.SOLUTION: A signal EQ is started simultaneously with a precharging start. Thus, transistors 201-328 and R201-202 are turned on, and data lines HON1-HON128 and reference lines REF1-REF2 are quickly charged by a precharge circuit 401 via a common line COM. As the data lines and the reference lines are connected in common via the transistors 201-328 and R201-R202 to be equalized, the data lines and the reference lines are uniformly charged. As the data lines and the reference lines are uniformly charged at a high speed, high-speed reading can be performed within a short time.
摘要翻译：要解决的问题：提供一种能够减小参考侧的芯片面积并进行高速读取的非易失性存储器。
解决方案：信号EQ与预充电开始同时启动。因此，晶体管201-328和R201-202导通，并且数据线HON1-HON128和参考线REF1-REF2通过公共线COM被预充电电路401快速充电。由于数据线和参考线通过晶体管201-328和R201-R202共同连接以进行均衡，所以数据线和参考线均匀地充电。随着数据线和参考线被高速均匀充电，可以在短时间内执行高速读取。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2007226957A Semiconductor device and nonvolatile semiconductor storage device 有权
标题翻译：半导体器件和非线性半导体存储器件
公开(公告)号：JP2007226957A
公开(公告)日：2007-09-06
申请号：JP2007062621
申请日：2007-03-12
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： HONDA YASUHIKO , KATO HIDEO , SAITO SAKATOSHI , KURIYAMA MASAO , HARA NORIMASA , IKEDA HISAFUMI , HIRAMATSU TATSUYA
IPC分类号： G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a flash memory which has a plurality of cores being sets of blocks to be used as units of data erasure, and enables concurrent execution of data write or erase operation in an arbitrary core, and of data read operation in other arbitrary cores. SOLUTION: In a memory cell array 1, a plurality of cores are arranged, wherein a memory cell range used as a unit for data erasure is made one block, and a set of one or a plurality of blocks is made one core. It is equipped with a core selection means for selection of arbitrary number of cores to perform data writing/erasing, performs writing data to a selected memory cell in a selected core based on a write command, and performs data erase of the selected block in the selected core based on an erase command. A free core method which enables data read to the memory cell in the core which is not selected is realized, while data writing/erasing is performed to a selected core with a core selection means. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有多个核的闪速存储器，作为用作数据擦除单位的块组，并且能够在任意的核心中并行执行数据写入或擦除操作，以及数据在其他任意内核读操作。解决方案：在存储单元阵列1中，布置多个核，其中将用作数据擦除的单位的存储单元范围制成一个块，并将一个或多个块的集合制成一个核。配备有用于选择任意数量的核以执行数据写入/擦除的核心选择装置，基于写入命令对所选择的核心中的所选存储单元执行写入数据，并且在所选择的核心中执行数据擦除基于擦除命令选择的内核。实现了对具有核心选择装置对所选核心执行数据写入/擦除的能够实现对未选择的核心中的存储单元的数据读取的自由核心方法。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006004496A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2006004496A
公开(公告)日：2006-01-05
申请号：JP2004178492
申请日：2004-06-16
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO SAKATOSHI
IPC分类号： G11C29/14 , G01R31/28 , G11C16/02
摘要： PROBLEM TO BE SOLVED: To efficiently perform a W/E (Write/Enable) test targeting a flash memory etc. with a simple procedure. SOLUTION: A semiconductor storage device is provided with a memory cell array 1 having a plurality of blocks, each of which comprises a plurality of memory cells, a column selection circuit 2, a column decoder 3, a row decoder 4, a block decoder 5, a protect ROM decoder 6, a multiplexer 7, an address decoder 8, an address counter 9, a final address detection circuit 10, a timer 11, a voltage generation circuit 12, a protect ROM 13, a protect circuit 14, a verify circuit 15, a verify bit register 16, a control circuit 17, a test circuit 18, a sense amplifier 19, a data input register 20, an input/output buffer 21, a command register 22, a clock generation circuit 23, a W/E test determination circuit 24, a W/E counter 25, a W/E counter comparator 26, a cycle counter 27, a configuration ROM 28, and a cycle comparator 29. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：以简单的程序有效地执行针对闪存等的W / E（写入/启用）测试。解决方案：半导体存储装置设置有具有多个块的存储单元阵列1，每个块包括多个存储单元，列选择电路2，列解码器3，行解码器4，块解码器5，保护ROM解码器6，多路复用器7，地址解码器8，地址计数器9，最终地址检测电路10，定时器11，电压产生电路12，保护ROM13，保护电路14 ，验证电路15，验证位寄存器16，控制电路17，测试电路18，读出放大器19，数据输入寄存器20，输入/输出缓冲器21，命令寄存器22，时钟产生电路23 ，W / E测试确定电路24，W / E计数器25，W / E计数器比较器26，循环计数器27，配置ROM28和循环比较器29。版权所有（C）2006 ，JPO＆NCIPI

8. 发明专利

JP2005302230A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2005302230A
公开(公告)日：2005-10-27
申请号：JP2004120263
申请日：2004-04-15
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKAI HIDEYOSHI , SAITO SAKATOSHI
IPC分类号： G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To automatically delete data in a plurality of serially arranged memory block areas in block by simple address specification without specifying all target addresses in an NOR type flash memory. SOLUTION: In the NOR type flash memory capable of deleting blocks BLK0 to BLK255 as the memory areas of the minimum deletion unit in block and performing separate operations by simultaneously accessing by every bank as a collection using the plurality of blocks as a unit, it is equipped with a command decoder 11 which generates a signal for controlling for automatically performing data deletion of the plurality of blocks in a bank when a command for specifying a bank deletion mode is inputted and generates a signal for automatically performing the data deletion of the plurality of blocks continuous over an area bank in a deletion target when a command for specifying an area deletion mode is inputted. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过简单的地址指定自动删除块中的多个串行排列的存储块区域中的数据，而不指定NOR型闪速存储器中的所有目标地址。解决方案：在能够删除块BLK0至BLK255的NOR型闪速存储器中，作为块中的最小删除单元的存储区域，并且通过使用多个块作为单元通过每个存储体同时访问作为集合来执行单独的操作配备有命令解码器11，当指定存储体删除模式的命令被输入时，该命令解码器11产生用于控制自动执行存储体中的多个块的数据删除的信号的信号，并产生用于自动执行数据删除的信号当输入用于指定区域删除模式的命令时，在删除目标中的区域组上连续的多个块。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2007207346A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2007207346A
公开(公告)日：2007-08-16
申请号：JP2006025043
申请日：2006-02-01
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： KONO TOMOHITO , SAITO SAKATOSHI
IPC分类号： G11C29/06 , G01R31/28 , G01R31/30 , G11C16/02
CPC分类号： G11C29/34 , G11C16/04 , G11C2029/1204 , G11C2029/1802 , G11C2029/2602
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which has a nonvolatile semiconductor memory capable of performing a bit line stress test even without any circuit for bit line stress test. SOLUTION: The device is provided with a first write-in load circuit I/O giving a potential in accordance with write-in data to even number bit lines during data write-in, and a second write-in load circuit I/O giving a potential in accordance with write-in data to odd number bit lines during data write-in, write-in high voltage is applied to even number bit lines and add number bit lines from the first and the second write-in load circuit during all bit stress test, the write-in high voltage is applied to the even number bit line from the first write-in load circuit during even bit stress test, a potential being lower than the write-in high voltage is applied to the odd number bit line from the second write-in load circuit, the lower potential is applied from the first write-in load circuit during odd bit stress test, and the write-in high voltage is applied to the odd number bit line from the second write-in load circuit. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体集成电路器件，其具有能够进行位线应力测试的非易失性半导体存储器，即使没有用于位线应力测试的任何电路。解决方案：在数据写入期间，该器件被提供有第一写入负载电路I / O <0>，其根据写入数据给偶数位线提供电位，并且第二写入负载电路I / O <8>在数据写入期间根据写入数据给奇数位线提供电位，写入高电压被施加到偶数位线，并且从第一位和第在所有位应力测试期间的第二个写入负载电路，在偶数位应力测试期间，写入高电压被施加到来自第一写入负载电路的偶数位线，电位低于写入从第二写入负载电路将高电压施加到奇数位线，在奇数位应力测试期间从第一写入负载电路施加较低电位，并将写入高电压施加到奇数位来自第二写入负载电路的数位位线。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2007164839A Nonvolatile semiconductor memory device and its self-test method 有权
标题翻译：非线性半导体存储器件及其自检方法
公开(公告)号：JP2007164839A
公开(公告)日：2007-06-28
申请号：JP2005356447
申请日：2005-12-09
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO SAKATOSHI
IPC分类号： G11C29/12 , G01R31/28 , G11C29/44
CPC分类号： G11C16/0416 , G11C16/04 , G11C16/3459 , G11C29/16 , G11C29/44 , G11C29/48 , G11C29/765 , G11C2029/0409 , G11C2029/1208 , G11C2229/723
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and its self-test method, in which a test time can be shortened.
SOLUTION: A test signal storing part 24A is constituted of erasable and writable storage means, and stores test information required for executing a test. A decoder 24B for BIST decodes a test command inputted to an interface 23 for BIST and selects test information stored in the test signal storage part 24A. A sense amplifier 18 reads out test information selected by the decoder 24B for BIST from the test signal storage part 24A, and a test signal register 19 holds the test information. A control circuit 14 controls test operation about whether main body memory cells 20A are operated normally or not based on the test information held in the test signal register 19. When the main body memory cells 20A are not operated normally, a defective block register 20C stores that the main body memory cells 20A are defective.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以缩短测试时间的非易失性半导体存储器件及其自检方法。解决方案：测试信号存储部分24A由可擦除和可写存储装置构成，并存储执行测试所需的测试信息。用于BIST的解码器24B对输入到BIST的接口23的测试命令进行解码，并选择存储在测试信号存储部分24A中的测试信息。读出放大器18从测试信号存储部分24A读取由解码器24B选择的用于BIST的测试信息，并且测试信号寄存器19保存测试信息。控制电路14基于保持在测试信号寄存器19中的测试信息来控制主体存储单元20A是否正常操作的测试操作。当主体存储单元20A不正常地操作时，缺陷块寄存器20C存储主体存储单元20A有缺陷。版权所有（C）2007，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式