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1. 发明授权

US06944003B2 Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system 失效
标题翻译：具有电压检测电路和信号发射和接收系统的半导体集成电路
公开(公告)号：US06944003B2
公开(公告)日：2005-09-13
申请号：US10365527
申请日：2003-02-13
申请人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
发明人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
IPC分类号： G01R31/28 , H01L21/66 , H02H9/04 , H02H3/24
CPC分类号： H02H9/046
摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.
摘要翻译：第一半导体集成电路通过电缆连接到第二半导体集成电路。在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作强制。因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。因此，在低电压条件下可以进行运行评估。

2. 发明授权

US06201412B1 Semiconductor integrated circuit with driver stabilization using parasitic capacitance 失效
标题翻译：具有驱动器稳定的半导体集成电路使用寄生电容
公开(公告)号：US06201412B1
公开(公告)日：2001-03-13
申请号：US09123902
申请日：1998-07-28
申请人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
发明人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
IPC分类号： H03K190175
CPC分类号： H03K19/01707
摘要： The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.
摘要翻译：本发明的半导体集成电路包括：驱动器，其包括用于驱动负载的MOS晶体管; 以及用于稳定由于MOS晶体管的栅极 - 源极寄生电容而在MOS晶体管的源极处的电压变化的稳定器。

3. 发明授权

US5764566A Static random access memory capable of reducing stendly power consumption and off-leakage current 失效
标题翻译：静态随机存取存储器能够降低待机功耗和漏电流
公开(公告)号：US5764566A
公开(公告)日：1998-06-09
申请号：US893682
申请日：1997-07-11
申请人： Hironori Akamatsu , Toru Iwata , Hisakazu Kotani
发明人： Hironori Akamatsu , Toru Iwata , Hisakazu Kotani
IPC分类号： G11C11/412 , G11C11/417 , G11C11/413
CPC分类号： G11C11/412 , G11C11/417
摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.
摘要翻译：当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。结果，接地电源线的电压从电源VSS的电压增加。因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

4. 发明授权

US06633607B1 Semiconductor device having a plurality of semiconductor chips connected together by a bus 有权
标题翻译：具有通过总线连接在一起的多个半导体芯片的半导体装置
公开(公告)号：US06633607B1
公开(公告)日：2003-10-14
申请号：US09249695
申请日：1999-02-12
申请人： Hironori Akamatsu , Toru Iwata , Hiroyuki Yamauchi
发明人： Hironori Akamatsu , Toru Iwata , Hiroyuki Yamauchi
IPC分类号： H03K904
CPC分类号： H03M9/00 , H04L25/49
摘要： A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.
摘要翻译：一种半导体器件包括：发送部分; 以及接收部分，其中所述发送部分和所述接收部分通过总线相互连接，所述发送部分包括用于对包括多个比特的数据进行编码的编码部分，以产生指示至少的位置的比特位置信息从包含在数据中的多个比特中选择一个比特，以及用于将比特位置信息输出到总线上的输出部分，并且接收部分包括用于从总线接收比特位置信息的输入部分和解码用于解码位位置信息以产生数据。

5. 发明授权

US06191632B1 Clock generation circuit and semiconductor integrated circuit 有权
标题翻译：时钟发生电路和半导体集成电路
公开(公告)号：US06191632B1
公开(公告)日：2001-02-20
申请号：US09359727
申请日：1999-07-23
申请人： Toru Iwata , Hironori Akamatsu
发明人： Toru Iwata , Hironori Akamatsu
IPC分类号： H03K300
CPC分类号： H03K5/153 , G06F1/10 , H03K5/133
摘要： A clock generation circuit comprises a clock wiring having opposed first and second ends, through which a clock is transmitted from the first end to the second end, and a plurality of clock phase adjustment circuits for generating internal clocks in accordance with the clock supplied from the clock wiring. Each of the clock phase adjustment circuits comprises a first-end side terminal and a second-end side terminal which are connected to a first-end side point and a second-end side point of the circuit, respectively, the points being positioned on both sides of a reference point of the clock wiring; a delay line for delaying a clock supplied from one of the terminals and outputting an internal clock; and a delay control circuit for performing feedback control on a delay of the clock in the delay means in accordance with the phase of the clock supplied from the other terminal so that the phase of the internal clock matches the phase of the clock at the reference point of the cock wiring. Therefore, regardless of the distances from the first end (clock input end) of the clock wiring to the respective clock phase adjustment circuits, internal clocks of the same phase are output from the clock phase adjustment circuits.
摘要翻译：时钟发生电路包括具有相对的第一和第二端的时钟布线，通过该时钟布线从第一端发送到第二端，以及多个时钟相位调整电路，用于根据从第一端提供的时钟产生内部时钟时钟接线。每个时钟相位调整电路包括分别连接到电路的第一端侧点和第二端侧点的第一端侧端子和第二端侧端子，所述点位于两者上侧面参考点的时钟布线; 用于延迟从一个终端提供的时钟并输出内部时钟的延迟线; 以及延迟控制电路，用于根据从另一个终端提供的时钟的相位对延迟装置中的时钟的延迟执行反馈控制，使得内部时钟的相位与参考点的时钟的相位匹配的公鸡接线。因此，不管从时钟线的第一端（时钟输入端）到各时钟相位调整电路的距离，从时钟相位调整电路输出同相的内部时钟。

6. 发明授权

US6140864A Circuit for controlling leakage current in large scale integrated circuits 失效
标题翻译：用于控制大规模集成电路中的漏电流的电路
公开(公告)号：US6140864A
公开(公告)日：2000-10-31
申请号：US927061
申请日：1997-09-10
申请人： Takashi Hirata , Toru Iwata , Hironori Akamatsu
发明人： Takashi Hirata , Toru Iwata , Hironori Akamatsu
IPC分类号： G06F1/26 , G05F3/02
CPC分类号： G06F1/26
摘要： In an LSI circuit, respective voltages on power-source lines connected to the respective sources of transistors which are turned OFF in a circuit block in the standby state are controlled by a power-source-voltage control circuit to vary in response to variations in the threshold voltages of the transistors. Consequently, the differential voltage (Vgs-Vt) between the gate-to-source voltage Vgs of each of the transistors and the threshold voltage Vt thereof is held constant at a given value, so that an OFF-state leakage current flowing through the transistor in the circuit block in the standby state is reduced and held constant at a given value. What results is a reduction in the power consumption of the circuit block in the standby state.
摘要翻译：在LSI电路中，通过电源电压控制电路来控制在待机状态下在电路块中断开的与晶体管的各个源连接的电源线上的各个电压，以响应于晶体管的阈值电压。因此，每个晶体管的栅 - 源电压Vgs与其阈值电压Vt之间的差分电压（Vgs-Vt）保持恒定在给定值，使得流过晶体管的截止状态漏电流处于待机状态的电路块减小并保持恒定在给定值。在待机状态下电路块的功耗降低是什么结果。

7. 发明授权

US6009024A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US6009024A
公开(公告)日：1999-12-28
申请号：US46880
申请日：1998-03-24
申请人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
发明人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/06
摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.
摘要翻译：本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管，并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。

8. 发明授权

US06473873B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06473873B1
公开(公告)日：2002-10-29
申请号：US09206534
申请日：1998-12-07
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G06F1100
CPC分类号： G11C29/10 , G11C29/36 , H01L27/10897
摘要： A semiconductor memory device includes: a memory block including a plurality of memory cells; and a test pattern generation circuit for generating at least one test pattern for use in testing the memory block. A first bus line for coupling the memory block and the test pattern generation circuit has a larger width than that of a second bus line for coupling the memory block to the exterior of the semiconductor memory device.
摘要翻译：半导体存储器件包括：包括多个存储器单元的存储器块; 以及测试图案生成电路，用于生成用于测试存储块的至少一个测试图案。用于耦合存储块和测试图案生成电路的第一总线具有比用于将存储块耦合到半导体存储器件的外部的第二总线的宽度大的宽度。

9. 发明授权

US06400637B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06400637B1
公开(公告)日：2002-06-04
申请号：US09673419
申请日：2000-10-18
申请人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
发明人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
IPC分类号： G11C800
CPC分类号： G11C8/14 , G11C8/12 , G11C11/4087
摘要： Four memory banks (10 to 13), each having a hierarchical word line structure, are provided. If a particular mode for one of the memory banks is specified by a control packet (PKT), a mode recognizer (15) produces the leading edges of change-of-sub-word enable (SEN0-3) and change-of-column enable (CEN-3) signals with the logical level of change-of-main-word enable (MEN0-3) signal fixed. This is done to make activated ones of sub-word and column select lines changeable in each of the memory banks with the same main word line still selected. In this manner, the row access speeds increase for the respective memory banks.
摘要翻译：提供四个具有分层字线结构的存储体（10至13）。如果通过控制分组（PKT）指定存储器组中的一个的特定模式，则模式识别器（15）产生子字改变使能（SEN0-3）和列更改的前沿使能（CEN-3）信号与主字使能（MEN0-3）信号的逻辑电平固定。这样做是为了使具有相同主字线仍被选择的每个存储体中的子字和列选择线的激活的一个可变。以这种方式，各存储体的行访问速度增加。

10. 发明授权

US06246627B1 Semiconductor device capable of cutting off a leakage current in a defective array section and method thereof 有权
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置及其方法
公开(公告)号：US06246627B1
公开(公告)日：2001-06-12
申请号：US09397239
申请日：1999-09-16
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C514
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

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