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1. 发明申请

US20110309439A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110309439A1
公开(公告)日：2011-12-22
申请号：US13052254
申请日：2011-03-21
申请人： Tomoko Matsudai , Koichi Endo , Kumiko Sato , Norio Yasuhara
发明人： Tomoko Matsudai , Koichi Endo , Kumiko Sato , Norio Yasuhara
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/0623 , H01L29/1045 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, a first conductivity-type region, a second conductivity-type source region, a gate insulating film and a gate electrode. The first conductivity-type region is provided in an upper layer portion of the semiconductor substrate. The second conductivity-type source region and a second conductivity-type drain region are arranged by being separated from each other in an upper layer portion of the first conductivity-type region. The gate insulating film is provided on the semiconductor substrate. The gate electrode is provided on the gate insulating film. An effective concentration of impurities in a channel region corresponding to a region directly below the gate electrode in the first conductivity-type region has a maximum at an interface between the gate insulating film and the channel region, and decreases toward a lower part of the channel region.
摘要翻译：根据一个实施例，半导体器件包括半导体衬底，第一导电类型区域，第二导电型源极区域，栅极绝缘膜和栅极电极。第一导电型区域设置在半导体衬底的上层部分中。第二导电型源极区域和第二导电型漏极区域通过在第一导电类型区域的上层部分中彼此分离而布置。栅极绝缘膜设置在半导体衬底上。栅电极设置在栅极绝缘膜上。与第一导电型区域中的栅电极正下方的区域对应的沟道区域中的杂质的有效浓度在栅极绝缘膜与沟道区域之间的界面处具有最大值，并且朝向沟道的下部逐渐减小地区。

2. 发明申请

US20110095369A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110095369A1
公开(公告)日：2011-04-28
申请号：US12878979
申请日：2010-09-09
申请人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
发明人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
IPC分类号： H01L29/772
CPC分类号： H01L29/0692 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.
摘要翻译：根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。

3. 发明授权

US08362554B2 MOSFET semiconductor device with backgate layer and reduced on-resistance 失效
标题翻译：具有背栅层和降低导通电阻的MOSFET半导体器件
公开(公告)号：US08362554B2
公开(公告)日：2013-01-29
申请号：US12878979
申请日：2010-09-09
申请人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
发明人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
IPC分类号： H01L29/78
CPC分类号： H01L29/0692 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.
摘要翻译：根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。

4. 发明申请

US20100096696A1 SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR FOR USE AS A HIGH-SPEED SWITCHING DEVICE AND A POWER DEVICE 有权
标题翻译：包括用作高速开关器件和功率器件的场效应晶体管的半导体器件
公开(公告)号：US20100096696A1
公开(公告)日：2010-04-22
申请号：US12645072
申请日：2009-12-22
申请人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
发明人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译：在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

5. 发明授权

US07692242B2 Semiconductor device used as high-speed switching device and power device 失效
标题翻译：半导体器件用作高速开关器件和功率器件
公开(公告)号：US07692242B2
公开(公告)日：2010-04-06
申请号：US11505337
申请日：2006-08-17
申请人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
发明人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
IPC分类号： H01L29/04 , H01L29/06
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译：在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。第一导电类型的源区形成在高电阻层的表面区域上。第一导电类型的漏极区域形成在与源极区域一定距离处。在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

6. 发明申请

US20100006936A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100006936A1
公开(公告)日：2010-01-14
申请号：US12476147
申请日：2009-06-01
申请人： Tomoko Matsudai , Norio Yasuhara , Kazutoshi Nakamura
发明人： Tomoko Matsudai , Norio Yasuhara , Kazutoshi Nakamura
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L21/266 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.
摘要翻译：半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

7. 发明授权

US07589389B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US07589389B2
公开(公告)日：2009-09-15
申请号：US12264580
申请日：2008-11-04
申请人： Tomoko Matsudai , Norio Yasuhara
发明人： Tomoko Matsudai , Norio Yasuhara
IPC分类号： H01L23/58
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/66681 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

8. 发明授权

US07473978B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07473978B2
公开(公告)日：2009-01-06
申请号：US11502387
申请日：2006-08-11
申请人： Tomoko Matsudai , Norio Yasuhara
发明人： Tomoko Matsudai , Norio Yasuhara
IPC分类号： H01L23/58
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/66681 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.
摘要翻译：一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。

9. 发明申请

US20070034985A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070034985A1
公开(公告)日：2007-02-15
申请号：US11502387
申请日：2006-08-11
申请人： Tomoko Matsudai , Norio Yasuhara
发明人： Tomoko Matsudai , Norio Yasuhara
IPC分类号： H01L23/58
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/66681 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.
摘要翻译：一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。

10. 发明授权

US5985708A Method of manufacturing vertical power device 失效
标题翻译：垂直功率器件的制造方法
公开(公告)号：US5985708A
公开(公告)日：1999-11-16
申请号：US816596
申请日：1997-03-13
申请人： Akio Nakagawa , Naoharu Sugiyama , Tomoko Matsudai , Norio Yasuhara , Atsusi Kurobe , Hideyuki Funaki , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Akio Nakagawa , Naoharu Sugiyama , Tomoko Matsudai , Norio Yasuhara , Atsusi Kurobe , Hideyuki Funaki , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L27/12 , H01L29/73 , H01L29/739 , H01L29/786 , H01L21/8249
CPC分类号： H01L29/78696 , H01L27/1203 , H01L29/7317 , H01L29/7394 , H01L29/78612 , H01L29/78624 , H01L29/78639 , H01L29/78645 , H01L29/78687
摘要： A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.
摘要翻译：一种半导体装置，包括具有第一导电型半导体衬底的垂直型半导体器件，形成在半导体衬底的表面上的漏极层，形成在漏极层的表面上的漏电极，第二导电型基极层，所述半导体衬底的与所述漏极层相对的表面，选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层，形成在所述第一导电型源极层和所述第二导电型基极层上的源电极，以及通过栅极绝缘膜与第一导电型源极层，第二导电型基极层和半导体基板接触形成的栅电极，以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置不同于第二导电型基底层，和多晶半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域，其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。

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