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1. 发明申请

US20110309439A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110309439A1
公开(公告)日：2011-12-22
申请号：US13052254
申请日：2011-03-21
申请人： Tomoko Matsudai , Koichi Endo , Kumiko Sato , Norio Yasuhara
发明人： Tomoko Matsudai , Koichi Endo , Kumiko Sato , Norio Yasuhara
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/0623 , H01L29/1045 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, a first conductivity-type region, a second conductivity-type source region, a gate insulating film and a gate electrode. The first conductivity-type region is provided in an upper layer portion of the semiconductor substrate. The second conductivity-type source region and a second conductivity-type drain region are arranged by being separated from each other in an upper layer portion of the first conductivity-type region. The gate insulating film is provided on the semiconductor substrate. The gate electrode is provided on the gate insulating film. An effective concentration of impurities in a channel region corresponding to a region directly below the gate electrode in the first conductivity-type region has a maximum at an interface between the gate insulating film and the channel region, and decreases toward a lower part of the channel region.
摘要翻译：根据一个实施例，半导体器件包括半导体衬底，第一导电类型区域，第二导电型源极区域，栅极绝缘膜和栅极电极。第一导电型区域设置在半导体衬底的上层部分中。第二导电型源极区域和第二导电型漏极区域通过在第一导电类型区域的上层部分中彼此分离而布置。栅极绝缘膜设置在半导体衬底上。栅电极设置在栅极绝缘膜上。与第一导电型区域中的栅电极正下方的区域对应的沟道区域中的杂质的有效浓度在栅极绝缘膜与沟道区域之间的界面处具有最大值，并且朝向沟道的下部逐渐减小地区。

2. 发明申请

US20110095369A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110095369A1
公开(公告)日：2011-04-28
申请号：US12878979
申请日：2010-09-09
申请人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
发明人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
IPC分类号： H01L29/772
CPC分类号： H01L29/0692 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.
摘要翻译：根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。

3. 发明授权

US08362554B2 MOSFET semiconductor device with backgate layer and reduced on-resistance 失效
标题翻译：具有背栅层和降低导通电阻的MOSFET半导体器件
公开(公告)号：US08362554B2
公开(公告)日：2013-01-29
申请号：US12878979
申请日：2010-09-09
申请人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
发明人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
IPC分类号： H01L29/78
CPC分类号： H01L29/0692 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.
摘要翻译：根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。

4. 发明申请

US20120012930A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120012930A1
公开(公告)日：2012-01-19
申请号：US13109233
申请日：2011-05-17
申请人： Kumiko Sato , Hirofumi Hirasozu , Tomoko Matsudai
发明人： Kumiko Sato , Hirofumi Hirasozu , Tomoko Matsudai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1045 , H01L21/26513 , H01L21/26586 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, and first and second transistors. The substrate has a first conductivity type. The first and second transistors are provided on the substrate. The first and second transistors each include a gate electrode provided on the substrate, a gate insulating film provided between the substrate and the gate electrode, a source and a drain region of a second conductivity type, and a high-concentration channel region of the first conductivity type. The source and drain regions are provided in regions of an upper portion of the substrate. A region directly under the gate electrode is interposed between the regions. The high-concentration channel region is formed on a side of the source region of the region of the upper portion directly under the gate electrode. The high-concentration channel region has an effective impurity concentration higher than that of the upper portion.
摘要翻译：根据一个实施例，半导体器件包括半导体衬底以及第一和第二晶体管。衬底具有第一导电类型。第一和第二晶体管设置在基板上。第一和第二晶体管各自包括设置在基板上的栅极电极，设置在基板和栅电极之间的栅极绝缘膜，第二导电类型的源极和漏极区域以及第一导电类型的高浓度沟道区域导电类型。源极和漏极区域设置在衬底的上部的区域中。位于该栅极电极正下方的区域之间。高浓度沟道区域形成在栅电极正下方的上部区域的源区的一侧。高浓度通道区域的有效杂质浓度高于上部区域。

5. 发明申请

US20070269377A1 Method of Producing Partial Peptide of Enolase Protein from Plasmodium Falciparum 有权
公开(公告)号：US20070269377A1
公开(公告)日：2007-11-22
申请号：US11663962
申请日：2005-09-28
申请人： Hiroyuki Oku , Kazuto Omi , Kaisuke Kuriyama , Jyunya Yamamoto , Keiichi Yamada , Ryoichi Katakai , Kumiko Sato , Mamoru Suzuki , Shin-ichiro Kawazu , Shigeyuki Kano
发明人： Hiroyuki Oku , Kazuto Omi , Kaisuke Kuriyama , Jyunya Yamamoto , Keiichi Yamada , Ryoichi Katakai , Kumiko Sato , Mamoru Suzuki , Shin-ichiro Kawazu , Shigeyuki Kano
IPC分类号： A61K39/015 , A61K49/00 , A61P33/06 , C07K1/10 , G01N33/569
CPC分类号： G01N33/56905 , A61K39/00 , C07K14/445 , C12N9/88 , Y02A50/412
摘要： F The peptide production method of the present invention produces a peptide (SEQ ID NO: 1) of a protein from Plasmodium falciparum, which is effective as a malaria vaccine. The method produces the peptide of SEQ ID NO: 1 by linking the fragments (i) through (v) shown below: (v)Asn-Asn-Asp-Xaa;(SEQ ID NO: 2) (iv)Asp-Phe-Lys-Thr-Pro;(SEQ ID NO: 3) (iii)Asn-Lys-Thr-Tyr-Asp-Leu;(SEQ ID NO: 4) (ii)Phe-Tyr-Asn-Ser-Glu;(SEQ ID NO: 5) and (i)Xaa-Ala-Ser-Glu,(SEQ ID NO: 6) where ‘Xaa’ in (i) and (v) represents zero or any arbitrary number of amino acid residues.

6. 发明授权

US07713926B2 Method of producing partial peptide of enolase protein from Plasmodium falciparum 有权
标题翻译：从恶性疟原虫生产烯醇酶蛋白质部分肽的方法
公开(公告)号：US07713926B2
公开(公告)日：2010-05-11
申请号：US11663962
申请日：2005-09-28
申请人： Hiroyuki Oku , Kazuto Omi , Keisuke Kuriyama , Jyunya Yamamoto , Keiichi Yamada , Ryoichi Katakai , Kumiko Sato , Mamoru Suzuki , Shin-ichiro Kawazu , Shigeyuki Kano
发明人： Hiroyuki Oku , Kazuto Omi , Keisuke Kuriyama , Jyunya Yamamoto , Keiichi Yamada , Ryoichi Katakai , Kumiko Sato , Mamoru Suzuki , Shin-ichiro Kawazu , Shigeyuki Kano
IPC分类号： A61K38/00 , C07K1/00
CPC分类号： G01N33/56905 , A61K39/00 , C07K14/445 , C12N9/88 , Y02A50/412
摘要： The peptide production method of the present invention produces a peptide (SEQ ID NO: 1) of a protein from Plasmodium falciparum, which is effective as a malaria vaccine. The method produces the peptide of SEQ ID NO: 1 by linking the fragments (i) through (v) shown below: (v) Asn-Asn-Asp-Xaa (SEQ ID NO: 2); (iv) Asp-Phe-Lys-Thr-Pro (SEQ ID NO: 3); (iii) Asn-Lys-Thr-Tyr-Asp-Leu (SEQ ID NO: 4); (ii) Phe-Tyr-Asn-Ser-Glu (SEQ ID NO: 5); and (i) Xaa-Ala-Ser-Glu (SEQ ID NO: 6), where ‘Xaa’ in (i) and (v) represents zero or any arbitrary number of amino acid residues.
摘要翻译：本发明的肽生产方法产生作为疟疾疫苗有效的来自恶性疟原虫的蛋白质的肽（SEQ ID NO：1）。该方法通过连接如下所示的片段（i）至（v）产生SEQ ID NO：1的肽：（v）Asn-Asn-Asp-Xaa（SEQ ID NO：2）; （iv）Asp-Phe-Lys-Thr-Pro（SEQ ID NO：3）; （iii）Asn-Lys-Thr-Tyr-Asp-Leu（SEQ ID NO：4）; （ii）Phe-Tyr-Asn-Ser-Glu（SEQ ID NO：5）; 和（i）Xaa-Ala-Ser-Glu（SEQ ID NO：6），其中（i）和（v）中的“Xaa”表示0或任意数目的氨基酸残基。

7. 发明授权

US4902477A Annalytical element for quantitative analysis of bilirubin 失效
标题翻译：胆红素定量分析的分析要素
公开(公告)号：US4902477A
公开(公告)日：1990-02-20
申请号：US273631
申请日：1988-11-17
申请人： Harumi Katsuyama , Shigeki Kageyama , Kumiko Sato
发明人： Harumi Katsuyama , Shigeki Kageyama , Kumiko Sato
IPC分类号： G01N31/22 , G01N33/52 , G01N33/72
CPC分类号： G01N33/728 , G01N33/526 , Y10S436/903 , Y10T436/146666
摘要： An analytical element for quantitative analysis of bilirubin in a liquid sample by a diazo method, characterized in that the bilirubin detection reagent is a non-diffusive aryldiazonium salt having in the aryl group at least one substituent selected from the group consisting of an alkoxycarbonyl group, an alkylaminosulfonyl group and an alkylaminocarbonyl group.
摘要翻译：一种用于通过重氮法定量分析液体样品中的胆红素的分析元件，其特征在于，所述胆红素检测试剂是非扩散性芳基重氮盐，其在所述芳基中具有至少一个选自烷氧基羰基，烷基氨基磺酰基和烷基氨基羰基。

8. 发明授权

US06780026B2 Electrical junction box 有权
标题翻译：电接线盒
公开(公告)号：US06780026B2
公开(公告)日：2004-08-24
申请号：US09987584
申请日：2001-11-15
申请人： Kumiko Sato
发明人： Kumiko Sato
IPC分类号： H01R1200
CPC分类号： H05K7/026 , H01R9/226 , H02G3/086
摘要： The electrical junction box X includes an upper cover 1, a distributing board 4 fitted with a busbar 5, a wiring sheet 6, and the lower cover 10. The lower cover 10 is formed with a through-hole 8a which is inserted by a terminal 5′ of the busbar 5. The wiring sheet 6 is provided with a through-hole 7a through which the terminal 5′ of the busbar 5 is inserted. This allows a smaller assembling tolerance between the terminal 5′ of the busbar 5 and the through-hole 8a in combination of the wiring sheet 6b attached to the distributing board 4 with the lower cover 10.
摘要翻译：电接线盒X包括上盖1，配有母线5的布线板4，布线板6和下盖10.下盖10形成有通过端子插入的通孔8a 5'。布线板6设有通孔7a，母线5的端子5'穿过该通孔7a插入。这允许汇流条5的端子5'和通孔8a之间的较小的组装公差，其结合安装在分配板4上的布线板6b与下盖10。

9. 发明授权

US06386923B2 Assembling structure of electronic unit to electrical connecting box 有权
标题翻译：电子单元组合到电气接线盒的结构
公开(公告)号：US06386923B2
公开(公告)日：2002-05-14
申请号：US09734582
申请日：2000-12-13
申请人： Tomohiro Sugiura , Kumiko Sato
发明人： Tomohiro Sugiura , Kumiko Sato
IPC分类号： H01R1364
CPC分类号： H02G3/16 , Y10S439/948
摘要： An assembling structure of an electronic unit to an electrical connecting box is provided. This assembling structure is provided with a miss-connection preventing portion on at least one of an electrical connecting box and an electronic unit combined to each other. The miss-connecting preventing portion is put in an interfering state with the mating side member to prevent the combination thereof when the two are combined improperly. The miss-connection prevention portion is provided at a peripheral wall portion of the electronic unit so that it interferes with a peripheral wall portion of the electrical connecting box when combination of the electrical connecting box and the electronic unit is improper.
摘要翻译：提供电子单元到电接线盒的组装结构。该组装结构在电连接箱和彼此组合的电子单元中的至少一个上设置有错过连接防止部。与错误接合防止部分处于与配合侧部件的干涉状态，以防止两者组合不正确时的组合。未连接防止部设置在电子单元的周壁部，使得当电连接盒和电子单元的组合不正确时，其与电连接盒的周壁部分干涉。

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