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1. 发明授权

US08252672B2 Silicon carbide semiconductor device comprising silicon carbide layer and method of manufacturing the same 有权
标题翻译：包含碳化硅层的碳化硅半导体器件及其制造方法
公开(公告)号：US08252672B2
公开(公告)日：2012-08-28
申请号：US12267040
申请日：2008-11-07
申请人： Tomokatsu Watanabe , Sunao Aya , Naruhisa Miura , Keiko Sakai , Shohei Yoshida , Toshikazu Tanioka , Yukiyasu Nakao , Yoichiro Tarui , Masayuki Imaizumi
发明人： Tomokatsu Watanabe , Sunao Aya , Naruhisa Miura , Keiko Sakai , Shohei Yoshida , Toshikazu Tanioka , Yukiyasu Nakao , Yoichiro Tarui , Masayuki Imaizumi
IPC分类号： H01L21/265
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/0485 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A method of manufacturing a silicon carbide semiconductor device having a silicon carbide layer, the method including a step of implanting at least one of Al ions, B ions and Ga ions having an implantation concentration in a range not lower than 1E19 cm−3 and not higher than 1E21 cm−3 from a main surface of the silicon carbide layer toward the inside of the silicon carbide layer while maintaining the temperature of the silicon carbide layer at 175° C. or higher, to form a p-type impurity layer; and forming a contact electrode whose back surface establishes ohmic contact with a front surface of the p-type impurity layer on the front surface of the p-type impurity layer.
摘要翻译：一种制造具有碳化硅层的碳化硅半导体器件的方法，该方法包括以下步骤：注入注入浓度在1E19cm-3以上的Al离子，B离子和Ga离子中的至少一种，而不是高于1E21cm-3，从碳化硅层的主表面朝向碳化硅层的内部，同时将碳化硅层的温度保持在175℃以上，形成p型杂质层; 以及形成其背面与p型杂质层前表面上的p型杂质层的前表面欧姆接触的接触电极。

2. 发明申请

US20090250705A1 SILICON CARBIDE SEMICONDUCTOR DEVICE COMPRISING SILICON CARBIDE LAYER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：含有碳化硅层的硅碳化硅半导体器件及其制造方法
公开(公告)号：US20090250705A1
公开(公告)日：2009-10-08
申请号：US12267040
申请日：2008-11-07
申请人： Tomokatsu WATANABE , Sunao Aya , Naruhisa Miura , Keiko Sakai , Shohei Yoshida , Toshikazu Tanioka , Yukiyasu Nakao , Yoichiro Tarui , Masayuki Imaizumi
发明人： Tomokatsu WATANABE , Sunao Aya , Naruhisa Miura , Keiko Sakai , Shohei Yoshida , Toshikazu Tanioka , Yukiyasu Nakao , Yoichiro Tarui , Masayuki Imaizumi
IPC分类号： H01L29/24 , H01L21/34
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/0485 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C. becomes lower than that in a case where the p++ region is formed by ion implantation at a temperature over 300° C. Further, this can avoid any process failure.
摘要翻译：碳化硅半导体器件的p基极欧姆接触由通过高浓度离子注入形成的p ++层和金属电极组成。由于在室温下进行的高浓度离子注入使p ++层的晶体显着降低，导致处理失败，所以使用在高温下注入的方法。在器件的开关损耗等方面，期望p基极欧姆接触的电阻率应该更低。在众所周知的技术中，在离子注入温度，欧姆接触电阻率和工艺故障之间的详细关系中没有提及。然后，在离子注入步骤中，碳化硅晶片的温度保持在175℃至300℃的范围内，更优选在175℃至200℃的范围内。在175℃〜300℃的温度范围内通过离子注入形成的p ++区域的p基极欧姆接触变得低于在超过300°的温度下通过离子注入形成p ++区域的情况下的p基极欧姆接触此外，这可以避免任何过程失败。

3. 发明申请

US20140077232A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20140077232A1
公开(公告)日：2014-03-20
申请号：US14116067
申请日：2012-03-07
申请人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Yukiyasu Nakao , Tomokatsu Watanabe , Masayoshi Tarutani , Yuji Ebiike , Masayuki Imaizumi , Sunao Aya
发明人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Yukiyasu Nakao , Tomokatsu Watanabe , Masayoshi Tarutani , Yuji Ebiike , Masayuki Imaizumi , Sunao Aya
IPC分类号： H01L29/16 , H01L29/78
CPC分类号： H01L29/1608 , H01L21/0485 , H01L29/0615 , H01L29/0638 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/7802 , H01L29/7811 , H01L29/7816 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.
摘要翻译：能够抑制阈值电压的时间变化的半导体器件及其制造方法。根据本发明的半导体器件包括形成在半导体衬底上的漂移层，形成在漂移层的表面层中的第一阱区彼此分开，形成在栅极绝缘膜上的栅极绝缘膜，在漂移层上延伸，每个选择性地形成在栅极绝缘膜上的栅极电极，穿过栅极绝缘膜并到达每个第一阱区域的内部的源极接触孔以及至少形成在第一阱区上的残留压应力层，源接触孔的侧表面，其中保持压缩应力。

4. 发明授权

US09093361B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09093361B2
公开(公告)日：2015-07-28
申请号：US14116067
申请日：2012-03-07
申请人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Yukiyasu Nakao , Tomokatsu Watanabe , Masayoshi Tarutani , Yuji Ebiike , Masayuki Imaizumi , Sunao Aya
发明人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Yukiyasu Nakao , Tomokatsu Watanabe , Masayoshi Tarutani , Yuji Ebiike , Masayuki Imaizumi , Sunao Aya
IPC分类号： H01L29/76 , H01L29/16 , H01L29/45 , H01L29/66 , H01L29/78 , H01L21/04 , H01L29/417 , H01L29/06
CPC分类号： H01L29/1608 , H01L21/0485 , H01L29/0615 , H01L29/0638 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/7802 , H01L29/7811 , H01L29/7816 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.
摘要翻译：能够抑制阈值电压的时间变化的半导体器件及其制造方法。根据本发明的半导体器件包括形成在半导体衬底上的漂移层，形成在漂移层的表面层中的第一阱区彼此分开，形成在栅极绝缘膜上的栅极绝缘膜，在漂移层上延伸，每个选择性地形成在栅极绝缘膜上的栅极电极，穿过栅极绝缘膜并到达每个第一阱区域的内部的源极接触孔以及至少形成在第一阱区上的残留压应力层，源接触孔的侧表面，其中保持压缩应力。

5. 发明申请

US20130288467A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130288467A1
公开(公告)日：2013-10-31
申请号：US13979564
申请日：2011-06-09
申请人： Yuji Ebiike , Takahiro Nakatani , Hiroshi Watanabe , Yoshio Fujii , Sunao Aya , Yoshiyuki Nakaki , Tsuyoshi Kawakami , Shuhei Nakata
发明人： Yuji Ebiike , Takahiro Nakatani , Hiroshi Watanabe , Yoshio Fujii , Sunao Aya , Yoshiyuki Nakaki , Tsuyoshi Kawakami , Shuhei Nakata
IPC分类号： H01L21/266
CPC分类号： H01L21/266 , H01L21/0465 , H01L23/544 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/872 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.
摘要翻译：能够抑制高电场的产生和防止发生电介质击穿的半导体装置及其制造方法。制造半导体器件的方法包括：（a）制备作为由第一导电类型的碳化硅半导体构成的接地的n +衬底，（b）通过使用抗蚀剂形成围绕n +衬底上的元件区域的凹陷结构图案，以及（c）通过通过抗蚀剂图案的杂质注入，在凹陷结构的凹槽底表面和凹陷侧表面中形成作为第二导电类型的杂质层的保护环注入层，以及凹陷结构被杂质层覆盖。

6. 发明授权

US5834142A Method of manufacturing X-ray mask and heating apparatus 失效
公开(公告)号：US5834142A
公开(公告)日：1998-11-10
申请号：US738287
申请日：1996-10-25
申请人： Hideki Yabe , Kenji Marumoto , Sunao Aya , Koji Kise , Hiroaki Sumitani , Takashi Hifumi , Hiroshi Watanabe
发明人： Hideki Yabe , Kenji Marumoto , Sunao Aya , Koji Kise , Hiroaki Sumitani , Takashi Hifumi , Hiroshi Watanabe
IPC分类号： G03F1/22 , H01L21/027 , H01L21/324 , G03F9/00
CPC分类号： G03F1/22
摘要： The X-ray mask manufactured according to the present invention can solve a problem that the thin film stress of the X-ray absorber cannot be made to be zero although the mean thin film stress throughout the X-ray absorber can be made to be zero. The thin film stress distribution over the X-ray absorber 4 after the X-ray absorber 4 has been formed on a silicon substrate 1 is measured, and then inputs of electric power to heaters 9a, 9b and 9c of a hot plate 8 are changed so as to heat the X-ray absorber 4 to temperatures according to a specified temperature distribution with which the thin film stress throughout the X-ray absorber can be made to be zero.

7. 发明授权

US5677090A Method of making X-ray mask having reduced stress 失效
标题翻译：制造应力减小的X射线掩模的方法
公开(公告)号：US5677090A
公开(公告)日：1997-10-14
申请号：US604678
申请日：1996-02-21
申请人： Kenji Marumoto , Hideki Yabe , Sunao Aya , Koji Kise , Kei Sasaki
发明人： Kenji Marumoto , Hideki Yabe , Sunao Aya , Koji Kise , Kei Sasaki
IPC分类号： B81B3/00 , B81C1/00 , G03F1/22 , G03F9/00
CPC分类号： G03F1/22 , B81C1/00666 , B81C2201/0167 , B81C2201/0169
摘要： A method of making a X-ray mask including: a step of forming a X-ray absorber above a substrate; a step of controlling a stress of the X-ray absorber by a predetermined condition; and wherein the predetermined condition for controlling the stress of the X-ray absorber formed above the substrate is determined by a measured value of a stress of a X-ray absorber formed on a monitor substrate.
摘要翻译：一种制造X射线掩模的方法，包括：在衬底上形成X射线吸收体的步骤; 控制X射线吸收体的应力为预定条件的步骤; 并且其中用于控制形成在基板上方的X射线吸收体的应力的预定条件由形成在监视器基板上的X射线吸收体的应力的测量值确定。

8. 发明授权

US09059086B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09059086B2
公开(公告)日：2015-06-16
申请号：US13979564
申请日：2011-06-09
申请人： Yuji Ebiike , Takahiro Nakatani , Hiroshi Watanabe , Yoshio Fujii , Sunao Aya , Yoshiyuki Nakaki , Tsuyoshi Kawakami , Shuhei Nakata
发明人： Yuji Ebiike , Takahiro Nakatani , Hiroshi Watanabe , Yoshio Fujii , Sunao Aya , Yoshiyuki Nakaki , Tsuyoshi Kawakami , Shuhei Nakata
IPC分类号： H01L21/265 , H01L21/76 , H01L21/266 , H01L29/06 , H01L29/16 , H01L29/66 , H01L21/04 , H01L23/544
CPC分类号： H01L21/266 , H01L21/0465 , H01L23/544 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/872 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.
摘要翻译：能够抑制高电场的产生和防止发生电介质击穿的半导体装置及其制造方法。制造半导体器件的方法包括：（a）制备作为由第一导电类型的碳化硅半导体构成的接地的n +衬底，（b）通过使用抗蚀剂形成围绕n +衬底上的元件区域的凹陷结构图案，以及（d）通过通过抗蚀剂图案的杂质注入，在凹部结构的凹部底面和凹部侧面中形成作为第二导电类型的杂质层的保护环注入层，以及凹陷结构被杂质层覆盖。

9. 发明授权

US06190808B1 X-ray mask and method of manufacturing the same 失效
标题翻译： X射线掩模及其制造方法
公开(公告)号：US06190808B1
公开(公告)日：2001-02-20
申请号：US09271297
申请日：1999-03-17
申请人： Koji Kise , Sunao Aya , Takaaki Murakami
发明人： Koji Kise , Sunao Aya , Takaaki Murakami
IPC分类号： G03F900
CPC分类号： G03F1/78 , G03F1/22 , G03F7/2051 , G03F7/70383 , G03F7/707
摘要： An X-ray mask including a transfer pattern having high accuracy is obtained. In a method of manufacturing the X-ray mask, an X-ray absorber film preventing transmission of an X-ray is formed on a substrate. A resist film is formed on the X-ray absorber film. The substrate is placed on a movable member. Steps of moving the movable member and irradiating the resist film with an energy beam are repeated for carrying out a drawing step of drawing a pattern on the resist film. Between the step of placing the substrate on the movable member and the drawing step, a step of holding a mask member including the resist film, the X-ray absorber film and the substrate to be in a state substantially identical to thermal equilibrium in the drawing step is carried out.
摘要翻译：获得包括高精度的转印图案的X射线掩模。在制造X射线掩模的方法中，在基板上形成防止透射X射线的X射线吸收膜。在X射线吸收膜上形成抗蚀剂膜。将基板放置在可动构件上。重复移动可动件并用能量束照射抗蚀剂膜的步骤，以进行在抗蚀剂膜上绘制图案的拉伸步骤。在将基板放置在可移动部件上的步骤和拉伸步骤之间，将包括抗蚀剂膜，X射线吸收膜和基板的掩模部件保持在与图中的热平衡基本相同的状态的步骤一步进行。

10. 发明授权

US06265113B1 Stress adjustment method of X-ray mask 失效
标题翻译： X射线掩模的应力调整方法
公开(公告)号：US06265113B1
公开(公告)日：2001-07-24
申请号：US09116334
申请日：1998-07-16
申请人： Hideki Yabe , Kaeko Kitamura , Kenji Marumoto , Sunao Aya , Koji Kise
发明人： Hideki Yabe , Kaeko Kitamura , Kenji Marumoto , Sunao Aya , Koji Kise
IPC分类号： G03F900
CPC分类号： G03F1/22
摘要： An X-ray absorber is deposited on a membrane. A stress adjust step is applied so that the average film stress of the X-ray absorber is 0. After patterning the X-ray absorber, the position accuracy of the pattern is measured. Then, a stress adjust process is applied to the patterned X-ray mask. Accordingly, a stress adjustment method is used to acquire an X-ray mask that has no pattern position offset of the X-ray absorber.
摘要翻译：在膜上沉积X射线吸收剂。施加应力调整步骤，使得X射线吸收体的平均膜应力为0.在对X射线吸收体进行图案化之后，测量图案的位置精度。然后，对图案化的X射线掩模施加应力调整处理。因此，使用应力调整方法来获取没有X射线吸收体的图案位置偏移的X射线掩模。

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