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1. 发明授权

US09059086B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09059086B2
公开(公告)日：2015-06-16
申请号：US13979564
申请日：2011-06-09
申请人： Yuji Ebiike , Takahiro Nakatani , Hiroshi Watanabe , Yoshio Fujii , Sunao Aya , Yoshiyuki Nakaki , Tsuyoshi Kawakami , Shuhei Nakata
发明人： Yuji Ebiike , Takahiro Nakatani , Hiroshi Watanabe , Yoshio Fujii , Sunao Aya , Yoshiyuki Nakaki , Tsuyoshi Kawakami , Shuhei Nakata
IPC分类号： H01L21/265 , H01L21/76 , H01L21/266 , H01L29/06 , H01L29/16 , H01L29/66 , H01L21/04 , H01L23/544
CPC分类号： H01L21/266 , H01L21/0465 , H01L23/544 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/872 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.
摘要翻译：能够抑制高电场的产生和防止发生电介质击穿的半导体装置及其制造方法。制造半导体器件的方法包括：（a）制备作为由第一导电类型的碳化硅半导体构成的接地的n +衬底，（b）通过使用抗蚀剂形成围绕n +衬底上的元件区域的凹陷结构图案，以及（d）通过通过抗蚀剂图案的杂质注入，在凹部结构的凹部底面和凹部侧面中形成作为第二导电类型的杂质层的保护环注入层，以及凹陷结构被杂质层覆盖。

2. 发明申请

US20130288467A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130288467A1
公开(公告)日：2013-10-31
申请号：US13979564
申请日：2011-06-09
申请人： Yuji Ebiike , Takahiro Nakatani , Hiroshi Watanabe , Yoshio Fujii , Sunao Aya , Yoshiyuki Nakaki , Tsuyoshi Kawakami , Shuhei Nakata
发明人： Yuji Ebiike , Takahiro Nakatani , Hiroshi Watanabe , Yoshio Fujii , Sunao Aya , Yoshiyuki Nakaki , Tsuyoshi Kawakami , Shuhei Nakata
IPC分类号： H01L21/266
CPC分类号： H01L21/266 , H01L21/0465 , H01L23/544 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/872 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.
摘要翻译：能够抑制高电场的产生和防止发生电介质击穿的半导体装置及其制造方法。制造半导体器件的方法包括：（a）制备作为由第一导电类型的碳化硅半导体构成的接地的n +衬底，（b）通过使用抗蚀剂形成围绕n +衬底上的元件区域的凹陷结构图案，以及（c）通过通过抗蚀剂图案的杂质注入，在凹陷结构的凹槽底表面和凹陷侧表面中形成作为第二导电类型的杂质层的保护环注入层，以及凹陷结构被杂质层覆盖。

3. 发明授权

US09202940B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09202940B2
公开(公告)日：2015-12-01
申请号：US14239375
申请日：2012-07-31
申请人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
发明人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
IPC分类号： H01L29/06 , H01L29/872 , H01L29/861 , H01L29/16
CPC分类号： H01L29/8725 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/8611 , H01L29/872
摘要： A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.
摘要翻译：具有高击穿电压和高可靠性的半导体器件，而不形成具有高定位精度的嵌入式注入层。半导体器件包括形成在第一导电类型的半导体层的表面层上的第二导电类型的有源区的基底，以构成半导体元件; 保护环作为多个第一导电类型的第一杂质区域，形成在半导体层的表面层上彼此间隔开以在平面图中分别包围基底; 以及作为第二导电类型的第二杂质区域的嵌入式注入层，其嵌入在半导体层的表面层中，以连接多个保护环的至少两个底部。

4. 发明申请

US20140203393A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140203393A1
公开(公告)日：2014-07-24
申请号：US14239375
申请日：2012-07-31
申请人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
发明人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
IPC分类号： H01L29/872
CPC分类号： H01L29/8725 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/8611 , H01L29/872
摘要： A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.
摘要翻译：具有高击穿电压和高可靠性的半导体器件，而不形成具有高定位精度的嵌入式注入层。半导体器件包括形成在第一导电类型的半导体层的表面层上的第二导电类型的有源区的基底，以构成半导体元件; 保护环作为多个第一导电类型的第一杂质区域，形成在半导体层的表面层上彼此间隔开以在平面图中分别包围基底; 以及作为第二导电类型的第二杂质区域的嵌入式注入层，其嵌入在半导体层的表面层中，以连接多个保护环的至少两个底部。

5. 发明申请

US20130140582A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130140582A1
公开(公告)日：2013-06-06
申请号：US13816511
申请日：2011-04-15
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
IPC分类号： H01L29/12 , H01L21/265
CPC分类号： H01L29/12 , H01L21/0465 , H01L21/265 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/66128 , H01L29/66143 , H01L29/66659 , H01L29/7835 , H01L29/8611 , H01L29/872
摘要： The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (101) including a plurality of P-type implantation layers having a relatively low concentration of P-type impurity is formed adjacent to an active region (2). The RESURF layer (101) includes a first RESURF layer (11), a second RESURF layer (12), a third RESURF layer (13), a fourth RESURF layer (14), and a fifth RESURF layer (15) that are arranged sequentially from the P-type base (2) side so as to surround the P-type base (2). The second RESURF layer (12) is configured with small regions (11′) having an implantation amount equal to that of the first RESURF layer (11) and small regions (13′) having an implantation amount equal to that of the third RESURF layer (13) being alternately arranged in multiple. The fourth RESURF layer (14) is configured with small regions (13′) having an implantation amount equal to that of the third RESURF layer (13) and small regions (15′) having an implantation amount equal to that of the fifth RESURF layer (15) being alternately arranged in multiple.
摘要翻译：半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。在活性区域（2）附近形成包括具有相对低浓度的P型杂质的多个P型注入层的RESURF层（101）。 RESURF层（101）包括第一RESURF层（11），第二RESURF层（12），第三RESURF层（13），第四RESURF层（14）和第五RESURF层（15）从P型基底（2）侧顺序地包围P型基底（2）。第二RESURF层（12）配置有具有等于第一RESURF层（11）的注入量的小区域（11'）和具有等于第三RESURF层的注入量的小区域（13'）（13）交替布置成多个。第四RESURF层（14）配置有具有等于第三RESURF层（13）的注入量的小区域（13'）和具有等于第五RESURF层的注入量的小区域（15'）（15）交替排列成多个。

6. 发明授权

US08716717B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08716717B2
公开(公告)日：2014-05-06
申请号：US13816511
申请日：2011-04-15
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
IPC分类号： H01L29/12
CPC分类号： H01L29/12 , H01L21/0465 , H01L21/265 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/66128 , H01L29/66143 , H01L29/66659 , H01L29/7835 , H01L29/8611 , H01L29/872
摘要： A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.
摘要翻译：在活性区域附近形成包括具有低浓度P型杂质的多个P型注入层的RESURF层。 RESURF层包括从P型基底侧依次布置以围绕P型基底的第一RESURF层，第二RESURF层，第三RESURF层，第四RESURF层和第五RESURF层。第二RESURF层配置有具有等于第一RESURF层的注入量的小区域，并且具有与第三RESURF层的注入量相等的注入量的小区域被交替排列成多个。第四RESURF层配置有具有等于第三RESURF层的注入量的小区域，并且具有与第五RESURF层的注入量相等的注入量的小区域被交替排列成多个。

7. 发明授权

US08314658B2 Power amplifier 有权
标题翻译：功率放大器
公开(公告)号：US08314658B2
公开(公告)日：2012-11-20
申请号：US12882592
申请日：2010-09-15
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Satoshi Yamakawa
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Satoshi Yamakawa
IPC分类号： H03F3/68
CPC分类号： H03F3/45076 , H03F3/19 , H03F3/211 , H03F3/602 , H03F2200/537 , H03F2200/541 , H03F2203/45731
摘要： A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.
摘要翻译：功率放大器包括设置在整体上呈圆形几何形状的基板上的多个初级电感器; 多个放大器对; 次级电感; 和连接线。每个放大器对耦合到相应的初级电感器的两端，并且分别放大并输出到相应的初级电感器作为差分输入信号给出的一对第一和第二信号。次级电感器以圆形几何形状邻近初级电感器提供，进一步组合并输出通过在每个初级电感器中组合第一和第二信号而产生的信号。连接布线设置在基板上的主电感器的内部，并且将各个初级电感器的中点彼此电耦合。

8. 发明申请

US20150279931A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150279931A1
公开(公告)日：2015-10-01
申请号：US14434388
申请日：2012-12-06
申请人： Ze CHEN , Tsuyoshi KAWAKAMI , Katsumi NAKAMURA
发明人： Ze Chen , Tsuyoshi Kawakami , Katsumi Nakamura
IPC分类号： H01L29/06
CPC分类号： H01L29/0619 , H01L29/0638 , H01L29/4236 , H01L29/7395 , H01L29/7397
摘要： The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers (12a˜120 are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers (12a˜120 respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [μm], and the number of the plurality of units is num, following relationships are satisfied. N≧(M×BV)γ, M=104 to 105, γ=0.55 to 1.95, SandL×num×Ecri≧2×α×BV, Ecri=2.0 to 3.0×105 [V/cm], α=100 to 101. Widths of the P-type ring layers (12a˜12f) of the plurality of units linearly decrease toward an outside of the termination region.
摘要翻译：终端区域包括环形区域（LNFLR）。多个环状P型环状层（12a〜120）规则地排列在环状区域（LNFLR）中，环状区域（LNFLR）被分割成多个包含多个P型环状层的单元 12a〜120，单位宽度恒定，环区（LNFLR）中P型杂质总数为N，目标耐受电压为BV [V]，各单位的宽度为SandL [μm ]，并且多个单元的数量为num，满足以下关系：N≥（M×BV）γ，M = 104〜105，γ= 0.55〜1.95，SandL×num×Ecri≥2×α×BV ，Ecri = 2.0〜3.0×105 [V / cm]，α= 100〜101.多个单元的P型环层（12a〜12f）的宽度向端子区域的外侧线性地减小。

9. 发明授权

US08330544B2 Power amplification circuit having transformer 有权
公开(公告)号：US08330544B2
公开(公告)日：2012-12-11
申请号：US13367121
申请日：2012-02-06
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Satoshi Yamakawa , Tetsuya Iida , Masao Kondo , Yutaka Hoshino
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Satoshi Yamakawa , Tetsuya Iida , Masao Kondo , Yutaka Hoshino
IPC分类号： H03F3/26
CPC分类号： H03F3/211 , H03F1/56 , H03F3/26 , H03F2200/537 , H03F2203/21139
摘要： In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

10. 发明授权

US08183930B2 Power amplifier device 失效
标题翻译：功率放大器装置
公开(公告)号：US08183930B2
公开(公告)日：2012-05-22
申请号：US13034216
申请日：2011-02-24
申请人： Tsuyoshi Kawakami , Kazuyasu Nishikawa
发明人： Tsuyoshi Kawakami , Kazuyasu Nishikawa
IPC分类号： H03F3/68
CPC分类号： H03F3/45183 , H03F3/195 , H03F2203/45352 , H03F2203/45364 , H03F2203/45731
摘要： This invention provides a power amplifier device that satisfies both of delivering a high output and reducing the chip area occupied by the power amplifier device. The power amplifier device formed over a substrate comprises primary inductors arranged in a generally circular geometry, a ground pattern, transistor pairs, and a secondary inductor. The ground pattern is provided to extend from a portion of a region inside the circular primary inductor into regions outside the primary inductor, when viewed from the direction perpendicular to the substrate, and grounded at a plurality of points in the regions outside the primary inductor. To both ends of each primary inductor, first main electrodes of first and second transistors forming a transistor pair in linkage with the primary inductor are coupled respectively. Second main electrodes of the first and second transistors are coupled to the ground pattern in the region inside the primary inductor and have electrical conduction to the respective plurality of points grounded.
摘要翻译：本发明提供一种功率放大器装置，其满足输出高输出和降低功率放大器装置占用的芯片面积的功能。形成在衬底上的功率放大器器件包括以大致圆形几何形状布置的初级电感器，接地图案，晶体管对和次级电感器。当从垂直于衬底的方向观察时，接地图案被设置成从圆形初级电感器内的区域的一部分延伸到主电感器外部的区域中，并且在初级电感器外部的区域中的多个点处接地。在每个初级电感器的两端分别耦合形成与主电感器连接的晶体管对的第一和第二晶体管的第一主电极。第一和第二晶体管的第二主电极在初级电感器内部的区域中耦合到接地图案，并且对相应的多个点接地进行导电。

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