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1. 发明授权

US5479620A Control unit modifying micro instructions for one cycle execution 失效
标题翻译：控制单元修改一个周期执行的微指令
公开(公告)号：US5479620A
公开(公告)日：1995-12-26
申请号：US103178
申请日：1993-08-09
申请人： Tokuzo Kiyohara , Kozo Kimura , Takahiro Watanabe
发明人： Tokuzo Kiyohara , Kozo Kimura , Takahiro Watanabe
IPC分类号： G06F9/22 , G06F9/26 , G06F9/318
CPC分类号： G06F9/3017 , G06F9/226 , G06F9/268 , G06F9/328
摘要： A control device includes a memory storing a plurality of micro instructions. A modifying information generator generates modifying information. A modifying unit receives one of the micro instructions and the modifying information from the memory and the modifying information generator respectively. The modifying unit modifies at least part of the one of the micro instructions with the modifying information.
摘要翻译：控制装置包括存储多个微指令的存储器。修改信息生成器生成修改信息。修改单元分别从存储器和修改信息生成器接收微指令之一和修改信息。修改单元利用修改信息修改微指令的至少一部分。

2. 发明申请

US20080215858A1 PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION 有权
标题翻译：能够有效执行计划的执行者和计划执行方法
公开(公告)号：US20080215858A1
公开(公告)日：2008-09-04
申请号：US12110539
申请日：2008-04-28
申请人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
发明人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

3. 发明申请

US20070286275A1 Integated Circuit For Video/Audio Processing 有权
标题翻译：用于视频/音频处理的整数电路
公开(公告)号：US20070286275A1
公开(公告)日：2007-12-13
申请号：US10599494
申请日：2005-04-01
申请人： Kozo Kimura , Tokuzo Kiyohara , Hiroshi Mizuno , Junji Michiyama , Tomohiko Kitamura , Ryoji Yamaguchi , Manabu Kuroda , Nobuhiko Yamada , Hideyuki Ohgose , Akifumi Yamana
发明人： Kozo Kimura , Tokuzo Kiyohara , Hiroshi Mizuno , Junji Michiyama , Tomohiko Kitamura , Ryoji Yamaguchi , Manabu Kuroda , Nobuhiko Yamada , Hideyuki Ohgose , Akifumi Yamana
IPC分类号： H04B1/66 , G06F13/12
CPC分类号： G06F13/4027 , H04N5/775 , H04N5/781 , H04N5/85 , H04N5/907 , H04N9/7921 , H04N9/8042
摘要： The present invention provides an integrated circuit for video/audio processing in which the design resources obtained by the development of video/audio devices can be used also for other types of video/audio devices. The integrated circuit comprises a microcomputer block 2 including a CPU, a stream I/O block 4 for inputting/outputting video and audio streams to and from an external device, a media processing block 3 for executing the media processing including at least one of the compression and decompression of the video and audio streams, etc. inputted to the stream I/O block 4, an AV IO block 5 for converting the video and audio streams subjected to the media processing in the media processing block 3 into video and audio signals and outputting these signals to the external device, etc, and a memory IF block 6 for controlling the data transfer between the microcomputer block 2, the stream I/C block 4, the media processing block 3 and the AV IO block 5 and an external memory 9.
摘要翻译：本发明提供了一种用于视频/音频处理的集成电路，其中通过开发视频/音频设备获得的设计资源也可以用于其他类型的视频/音频设备。该集成电路包括一个包括CPU的微处理器块2，用于向外部设备输入/输出视频和音频流的流I / O块4，用于执行媒体处理的媒体处理块3，包括至少一个输入到流I / O块4的视频和音频流等的压缩和解压缩，用于将经过媒体处理块3中的媒体处理的视频和音频流转换成视频和音频信号的AV IO块5 并将这些信号输出到外部设备等;以及存储器IF块6，用于控制微计算机块2，流I / C块4，媒体处理块3和AV IO块5之间的数据传输，以及外部记忆9。

4. 发明授权

US06212236B1 Image decoding apparatus 失效
标题翻译：图像解码装置
公开(公告)号：US06212236B1
公开(公告)日：2001-04-03
申请号：US09048190
申请日：1998-03-25
申请人： Hideshi Nishida , Kozo Kimura , Makoto Hirai , Tokuzo Kiyohara
发明人： Hideshi Nishida , Kozo Kimura , Makoto Hirai , Tokuzo Kiyohara
IPC分类号： H04N712
CPC分类号： H04N19/507 , H04N19/61
摘要： Bitstream analyzing unit 111 fetches a coded block pattern and a coded quantized DCT coefficient from each block in a bitstream. Entropy decoding unit 112 decodes the coded block pattern into a block pattern and decodes the coded quantized DCT coefficient into pairs of a run length and an effectiveness factor. Dequantization unit 115 generates orthogonal transformation coefficients from the pairs of a run length and an effectiveness factor. Inverse Discrete Cosine Transform (IDCT) unit 110 generates a difference image from the orthogonal transformation coefficients. Decode controlling unit 110 instructs first selecting unit 118 to select constants “0”output from first constant generating unit 117 when the image is a “skipped” block. Image storage unit 120 stores a plurality of reference frame pictures having been decoded. Image restoring unit 119 restores an original block by adding a decoded difference image to a reference block read from the reference frame pictures stored in the image storage unit 120.
摘要翻译：比特流分析单元111从比特流中的每个块获取编码块模式和编码的量化DCT系数。熵解码单元112将编码块模式解码为块模式，并将编码的量化DCT系数解码为游程长度和有效性因子对。去量化单元115从游程长度和有效性因子的对生成正交变换系数。逆离散余弦变换（IDCT）单元110从正交变换系数生成差分图像。当图像为“跳过”块时，解码控制单元110指示第一选择单元118选择从第一常数生成单元117输出的常数“0”。图像存储单元120存储已被解码的多个参考帧图像。图像恢复单元119通过将解码的差异图像添加到从存储在图像存储单元120中的参考帧图像中读取的参考块来恢复原始块。

5. 发明授权

US6075899A Image decoder and image memory overcoming various kinds of delaying factors caused by hardware specifications specific to image memory by improving storing system and reading-out system 失效
标题翻译：图像解码器和图像存储器通过改进存储系统和读出系统来克服由图像存储器特有的硬件规格引起的各种延迟因素
公开(公告)号：US6075899A
公开(公告)日：2000-06-13
申请号：US66308
申请日：1998-03-27
申请人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
发明人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： H04N5/907 , H04N9/64 , H04N19/00 , H04N19/423 , H04N19/426 , H04N19/44 , H04N19/46 , H04N19/503 , H04N19/59 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/85 , H04N19/91 , G06K9/46
CPC分类号： H04N5/907 , H04N19/42 , H04N19/423 , H04N19/61 , H04N9/64
摘要： An image memory stores a one-screen image by dividing the one-screen image into a plurality of image blocks which are each m pixels wide by n pixels high. The image memory has an array-like storage region storing s*t first chrominance components that compose one image block and s*t second chrominance components that compose the same image block in serial areas between a start area specified by a row address and a first column address and an end area specified by the same row address and a second column address (see FIG. 10). The storage region also stores m*n luminance components that compose the same image block in serial areas between a different start area specified by a different row address and a third column address and an end area are specified by the different row address and a fourth column address.
摘要翻译： PCT No.PCT / JP97 / 02995 Sec。 371日期：1998年4月27日 102（e）日期1998年4月27日PCT 1997年8月29日PCT公布。第WO98 / 09444号公报日期1998年3月5日图像存储器通过将单屏图像分成多个像素宽×高n个像素的图像块来存储单屏图像。图像存储器具有存储s * t个第一色度分量的阵列状存储区域，其构成一个图像块和s * t个第二色度分量，其在由行地址指定的起始区域和第一个列地址和由相同行地址和第二列地址指定的结束区域（参见图10）。存储区域还存储在由不同行地址指定的不同起始区域和第三列地址之间的串行区域中构成相同图像块的m * n个亮度分量，并且结束区域由不同的行地址和第四列地址。

6. 发明授权

US08719827B2 Processor and program execution method capable of efficient program execution 有权
标题翻译：处理器和程序执行方法能够高效地执行程序
公开(公告)号：US08719827B2
公开(公告)日：2014-05-06
申请号：US13179614
申请日：2011-07-11
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/46 , G06F9/00 , G06F1/00
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

7. 发明授权

US07934082B2 Information processing apparatus and exception control circuit 有权
标题翻译：信息处理装置和异常控制电路
公开(公告)号：US07934082B2
公开(公告)日：2011-04-26
申请号：US11658816
申请日：2005-08-19
申请人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
发明人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F9/48
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3861 , G06F9/3879 , G06F9/4812 , G06F2209/481
摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.
摘要翻译：信息处理装置执行异常处理程序与正常处理之间的切换。信息处理装置包括处理器，数据处理单元，其在从处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中，所述数据处理单元经由专用线与所述异常控制单元连接。数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器向处理器发出执行异常处理程序的中断请求。

8. 发明授权

US07386707B2 Processor and program execution method capable of efficient program execution 有权
标题翻译：处理器和程序执行方法能够高效地执行程序
公开(公告)号：US07386707B2
公开(公告)日：2008-06-10
申请号：US10338408
申请日：2003-01-08
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

9. 发明授权

US07315934B2 Data processor and program for processing a data matrix 有权
标题翻译：用于处理数据矩阵的数据处理器和程序
公开(公告)号：US07315934B2
公开(公告)日：2008-01-01
申请号：US10377328
申请日：2003-02-28
申请人： Hiroyuki Morishita , Atsushi Ito , Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara , Akira Miyoshi , Hiroshi Kadota
发明人： Hiroyuki Morishita , Atsushi Ito , Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara , Akira Miyoshi , Hiroshi Kadota
IPC分类号： G06F15/76
CPC分类号： G06F9/3012 , G06F9/30036 , G06F9/3824 , G06F9/3885
摘要： A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.
摘要翻译：数据处理器具有16个处理元件，每个处理元件包括寄存器文件和算术逻辑单元。网络单元连接处理元件的寄存器文件和处理元件的算术逻辑单元。网络单元具有选择器，用于同时执行多个数据传送，每个数据传输由一个处理元件的寄存器文件制成到另一个处理元件的操作单元。通过提供可以执行这种同时数据传输的该选择器，即使在操作数分配等中发生改变，也可以保持处理元件的处理效率。

10. 发明授权

US07079583B2 Media processing apparatus which operates at high efficiency 有权
公开(公告)号：US07079583B2
公开(公告)日：2006-07-18
申请号：US10007248
申请日：2001-10-24
申请人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
发明人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： H04N7/12
CPC分类号： H04N19/90 , H04N5/4401 , H04N21/426 , H04N21/42607 , H04N21/42653 , H04N21/42692 , H04N21/4302 , H04N21/4341
摘要： A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.

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