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1. 发明授权

US07079583B2 Media processing apparatus which operates at high efficiency 有权
公开(公告)号：US07079583B2
公开(公告)日：2006-07-18
申请号：US10007248
申请日：2001-10-24
申请人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
发明人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： H04N7/12
CPC分类号： H04N19/90 , H04N5/4401 , H04N21/426 , H04N21/42607 , H04N21/42653 , H04N21/42692 , H04N21/4302 , H04N21/4341
摘要： A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.

2. 发明授权

US06310921B1 Media processing apparatus which operates at high efficiency 失效
标题翻译：以高效率运行的媒体处理装置
公开(公告)号：US06310921B1
公开(公告)日：2001-10-30
申请号：US09055583
申请日：1998-04-06
申请人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
发明人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： H04N712
CPC分类号： H04N19/90 , H04N5/4401 , H04N21/426 , H04N21/42607 , H04N21/42653 , H04N21/42692 , H04N21/4302 , H04N21/4341
摘要： A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.
摘要翻译：媒体处理装置由用于执行由于外部因素而异步发生的输入/输出处理的I / O处理单元和用于执行主要用于解码存储在存储器中的数据流的解码处理的解码处理单元输入/输出处理。输入/输出处理包括接收异步输入的数据流，将输入的数据流存储在存储器中，并将数据流从存储器提供给解码处理单元。解码处理单元由主要对数据流执行条件判断的顺序处理单元和与压缩视频数据的标题分析相一致的压缩视频数据执行解码处理的例程处理单元构成，与顺序处理并行。因此，输入/输出处理装置和解码处理装置分别充有异步处理和解码处理，并且输入/输出处理装置和解码处理装置如在流水线处理中并行操作。结果，无论异步处理如何，解码处理装置都可以用于解码处理。因此，有效地执行包括流数据的输入处理，输入数据的解码处理和解码数据的输出处理的处理。

3. 发明授权

US06829302B2 Pixel calculating device 有权
标题翻译：像素计算装置
公开(公告)号：US06829302B2
公开(公告)日：2004-12-07
申请号：US10019498
申请日：2001-12-20
申请人： Hiroyuki Morishita , Kosuke Yoshioka , Hideshi Nishida , Makoto Hirai , Ryuji Matsuura , Toshiaki Tsuji , Kozo Kimura , Tokuzo Kiyohara
发明人： Hiroyuki Morishita , Kosuke Yoshioka , Hideshi Nishida , Makoto Hirai , Ryuji Matsuura , Toshiaki Tsuji , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： H04N712
CPC分类号： H04N19/80 , G06T3/4007 , G06T3/4023 , G06T5/20 , G06T2200/28
摘要： A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.
摘要翻译：一种对像素数据进行垂直滤波以便在垂直方向上减少帧数据的像素计算装置。像素计算装置包括用于解码压缩视频数据以产生帧数据的解码单元401，用于存储帧数据的帧存储器402，用于通过垂直滤波减少垂直方向上的帧数据以产生缩小图像的滤波单元403 用于存储从滤波单元403输出的缩小图像的缓冲存储器404，以及基于解码单元401的视频数据的解码状态和滤波单元403的帧数据的滤波状态来控制滤波单元403的控制单元406 ，因此在过滤单元403中不会发生溢出和欠载。

4. 发明授权

US06809777B2 Pixel calculating device 有权
标题翻译：像素计算装置
公开(公告)号：US06809777B2
公开(公告)日：2004-10-26
申请号：US10019419
申请日：2001-12-18
申请人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara , Makoto Hirai , Kozo Kimura , Ryuji Matsuura , Hiroyuki Morishita , Toshiaki Tsuji
发明人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara , Makoto Hirai , Kozo Kimura , Ryuji Matsuura , Hiroyuki Morishita , Toshiaki Tsuji
IPC分类号： H04N964
CPC分类号： H04N19/80 , G06T1/20 , G06T5/20
摘要： A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.
摘要翻译：用于执行垂直滤波的像素计算装置，其包括16个像素处理单元1至16以及存储16个像素数据和滤波器系数的输入缓冲器组22。每个像素处理单元使用从输入缓冲器组22提供的像素数据和滤波器系数来执行操作，然后从邻近的像素处理单元获取像素数据。使用所获取的像素数据由每个像素处理单元执行进一步的操作，并且累积运算结果。通过重复该获取和累积过程来进行过滤，抽头的数量由重复次数确定。

5. 发明授权

US6075899A Image decoder and image memory overcoming various kinds of delaying factors caused by hardware specifications specific to image memory by improving storing system and reading-out system 失效
标题翻译：图像解码器和图像存储器通过改进存储系统和读出系统来克服由图像存储器特有的硬件规格引起的各种延迟因素
公开(公告)号：US6075899A
公开(公告)日：2000-06-13
申请号：US66308
申请日：1998-03-27
申请人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
发明人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： H04N5/907 , H04N9/64 , H04N19/00 , H04N19/423 , H04N19/426 , H04N19/44 , H04N19/46 , H04N19/503 , H04N19/59 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/85 , H04N19/91 , G06K9/46
CPC分类号： H04N5/907 , H04N19/42 , H04N19/423 , H04N19/61 , H04N9/64
摘要： An image memory stores a one-screen image by dividing the one-screen image into a plurality of image blocks which are each m pixels wide by n pixels high. The image memory has an array-like storage region storing s*t first chrominance components that compose one image block and s*t second chrominance components that compose the same image block in serial areas between a start area specified by a row address and a first column address and an end area specified by the same row address and a second column address (see FIG. 10). The storage region also stores m*n luminance components that compose the same image block in serial areas between a different start area specified by a different row address and a third column address and an end area are specified by the different row address and a fourth column address.
摘要翻译： PCT No.PCT / JP97 / 02995 Sec。 371日期：1998年4月27日 102（e）日期1998年4月27日PCT 1997年8月29日PCT公布。第WO98 / 09444号公报日期1998年3月5日图像存储器通过将单屏图像分成多个像素宽×高n个像素的图像块来存储单屏图像。图像存储器具有存储s * t个第一色度分量的阵列状存储区域，其构成一个图像块和s * t个第二色度分量，其在由行地址指定的起始区域和第一个列地址和由相同行地址和第二列地址指定的结束区域（参见图10）。存储区域还存储在由不同行地址指定的不同起始区域和第三列地址之间的串行区域中构成相同图像块的m * n个亮度分量，并且结束区域由不同的行地址和第四列地址。

6. 发明授权

US07228064B2 Image decoding apparatus, recording medium which computer can read from, and program which computer can read 失效
标题翻译：图像解码装置，计算机可读取的记录介质，以及计算机可读取的程序
公开(公告)号：US07228064B2
公开(公告)日：2007-06-05
申请号：US10211716
申请日：2002-08-02
申请人： Yoshiyuki Wada , Makoto Hirai , Tokuzo Kiyohara , Kosuke Yoshioka , Hideshi Nishida , Yukiharu Ieda
发明人： Yoshiyuki Wada , Makoto Hirai , Tokuzo Kiyohara , Kosuke Yoshioka , Hideshi Nishida , Yukiharu Ieda
IPC分类号： H04N7/26 , H03N7/40
CPC分类号： H04N9/7921 , H04N5/78266 , H04N9/8042 , H04N9/8047 , H04N19/42
摘要： The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.
摘要翻译：本发明提供一种图像解码装置，其实现从由第一DCT块和MR组成的固定长度单元取出MR（宏块余数）的加速处理，而不增加成本。安装处理器3输出构成SB（同步块）的多个固定长度单元中的一个。首先，从固定长度单位的开始到包括在固定长度单位中的EOB（块末尾）的长度进行计算。然后将计算出的长度用作取出MR的偏移量。然后，包括在MR中的第二DCT块的结束部分与第二DCT块的对应开始部分组合，以便获得完整的第二DCT块。完整的第二DCT块被输出到可变长度码解码器13。

7. 发明授权

US07167520B2 Transcoder 失效
标题翻译：转码器
公开(公告)号：US07167520B2
公开(公告)日：2007-01-23
申请号：US10686237
申请日：2003-10-15
申请人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
发明人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
IPC分类号： H04B1/66
CPC分类号： G06T3/40 , H04N19/16 , H04N19/40 , H04N19/42 , H04N19/59 , H04N19/61
摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.
摘要翻译：一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。

8. 发明申请

US20050238095A1 Transcoder 失效
标题翻译：转码器
公开(公告)号：US20050238095A1
公开(公告)日：2005-10-27
申请号：US10686237
申请日：2003-10-15
申请人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
发明人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
IPC分类号： G06T3/40 , H04N7/12 , H04N7/26 , H04N7/46 , H04N7/50
CPC分类号： G06T3/40 , H04N19/16 , H04N19/40 , H04N19/42 , H04N19/59 , H04N19/61
摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.
摘要翻译：一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。

9. 发明授权

US06470376B1 Processor capable of efficiently executing many asynchronous event tasks 失效
标题翻译：处理器能够有效地执行许多异步事件任务
公开(公告)号：US06470376B1
公开(公告)日：2002-10-22
申请号：US09034198
申请日：1998-03-03
申请人： Takaharu Tanaka , Kiyoshi Maenobu , Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara
发明人： Takaharu Tanaka , Kiyoshi Maenobu , Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara
IPC分类号： G06F900
CPC分类号： G06F9/4881 , G06F9/30087 , G06F9/3009 , G06F9/3851 , H04N19/42 , H04N19/61
摘要： The counter 52 is set with an initial value of “1” and is a counter with a maximum value of “4”. This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1,2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value “4”, and when the values match, sets the task switching signal chg_task_ex at a “High” value, so that the processing switches to the execution of the next task.
摘要翻译：计数器52被设置为初始值“1”，并且是具有最大值“4”的计数器。该计数器52与时钟信号同步地增加由触发器51保持的计数值，使得计数值如进展1,2,3,4,1,2,3,4所示变化。指令解码控制单元11还使用该时钟信号来控制指令的执行，计数器52对由指令解码控制单元11进行的每个指令执行一次执行一次计数。比较器54将计数值由具有最大值“4”的计数器52计数，并且当该值匹配时，将任务切换信号chg_task_ex设置为“高”值，使得处理切换到下一任务的执行。

10. 发明授权

US06340973B1 Memory control unit and memory control method and medium containing program for realizing the same 有权
标题翻译：存储器控制单元和存储器控制方法以及包含用于实现该程序的介质
公开(公告)号：US06340973B1
公开(公告)日：2002-01-22
申请号：US09244036
申请日：1999-02-04
申请人： Toshiyuki Ochiai , Yosuke Furukawa , Yutaka Tanaka , Kozo Kimura , Makoto Hirai , Tokuzo Kiyohara , Hideshi Nishida
发明人： Toshiyuki Ochiai , Yosuke Furukawa , Yutaka Tanaka , Kozo Kimura , Makoto Hirai , Tokuzo Kiyohara , Hideshi Nishida
IPC分类号： G06F13372
CPC分类号： G06F13/1647 , G11C7/1072 , G11C7/22
摘要： A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data first transferred by read access. A command generator generates control commands in accordance with the control signals to control an SDRAM. At this time the command generator judges the number of transferred bytes to control so that the SDRAM executes instructions in order from an instruction which is the most efficient in data transfer. That is, in the case where data is read across a bank boundary, the command generator judges which is to be executed first between read processing in a bank 0 and active processing in a bank1, to control the SDRAM. A data processor mediates data transfer between the transfer-target unit and the SDRAM in accordance with the control commands. In this way, it is possible to issue commands so as to terminate data transfer in the minimum number of cycles in the case where data read processing is continuously performed to different banks. The number of cycles required for two continuous access (access to the bank 0 and the bank 1) can be thus reduced, thereby increasing effective transfer rates of the SDRAM.
摘要翻译：传输目标单元输出用于数据读取和数据写入的命令。地址生成器根据命令生成控制信号，并输出通过读取访问首先传送的数据的字节数。命令发生器根据控制信号产生控制命令以控制SDRAM。此时，命令生成器判断要进行控制的传送字节数，使得SDRAM从数据传输中最有效的指令按顺序执行指令。也就是说，在通过存储体边界读取数据的情况下，命令生成器判断在存储体0中的读取处理和存储体1中的有效处理之间首先执行哪个，以控制SDRAM。数据处理器根据控制命令介入转移目标单元和SDRAM之间的数据传输。以这种方式，可以发出命令，以便在数据读取的情况下以最小数量的周期终止数据传输不断对不同的银行进行处理。因此可以减少两次连续访问（对存储体0和存储体1的访问）所需的周期数，从而增加SDRAM的有效传输速率。

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