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1. 发明授权

US07848318B2 Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据发射器的串行器电路
公开(公告)号：US07848318B2
公开(公告)日：2010-12-07
申请号：US11364589
申请日：2006-02-27
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： H04Q11/00
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

2. 发明授权

US08570197B2 Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据发射器的串行器电路
公开(公告)号：US08570197B2
公开(公告)日：2013-10-29
申请号：US12953766
申请日：2010-11-24
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

3. 发明授权

US07659838B2 Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
公开(公告)号：US07659838B2
公开(公告)日：2010-02-09
申请号：US11359273
申请日：2006-02-21
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串器电路包括用于将串行数据转换成具有若干数据宽度的并行数据的电路。电路也可以在宽频率范围内的任何频率下工作。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

4. 发明申请

US20070030184A1 Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据发射器的串行器电路
公开(公告)号：US20070030184A1
公开(公告)日：2007-02-08
申请号：US11364589
申请日：2006-02-27
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

5. 发明申请

US20070043991A1 Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
公开(公告)号：US20070043991A1
公开(公告)日：2007-02-22
申请号：US11359273
申请日：2006-02-21
申请人： Toan Nguyen , Thungoc Tran , Sergey Shumarayev , Arch Zaliznyak , Tim Hoang , Ramanand Venkata , Chong Lee
发明人： Toan Nguyen , Thungoc Tran , Sergey Shumarayev , Arch Zaliznyak , Tim Hoang , Ramanand Venkata , Chong Lee
IPC分类号： G01R31/28
CPC分类号： H03M9/00
摘要： Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串器电路包括用于将串行数据转换成具有若干数据宽度的并行数据的电路。电路也可以在宽频率范围内的任何频率下工作。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

6. 发明申请

US20140035642A1 Techniques for Aligning and Reducing Skew in Serial Data Signals 有权
标题翻译：在串行数据信号中对齐和减少偏移的技术
公开(公告)号：US20140035642A1
公开(公告)日：2014-02-06
申请号：US13566882
申请日：2012-08-03
申请人： Ramanand Venkata , Henry Lui , Arch Zaliznyak
发明人： Ramanand Venkata , Henry Lui , Arch Zaliznyak
IPC分类号： H03K5/1534
CPC分类号： H03K5/1534
摘要： A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.
摘要翻译：一个电路包括第一和第二对准器电路和一个去歪斜电路。第一对准器电路可操作以将第一输入串行数据信号与控制信号对准以产生第一对准的串行数据信号。第二对准器电路可操作以将第二输入串行数据信号与控制信号对准以产生第二对准的串行数据信号。去偏置电路可操作以减少第一和第二对准的串行数据信号之间的偏差，以产生第一和第二输出串行数据信号。

7. 发明授权

US08581653B1 Techniques for providing clock signals in clock networks 有权
标题翻译：在时钟网络中提供时钟信号的技术
公开(公告)号：US08581653B1
公开(公告)日：2013-11-12
申请号：US13328784
申请日：2011-12-16
申请人： Victor Maruri , Arch Zaliznyak , Ramanand Venkata , Henry Y. Lui
发明人： Victor Maruri , Arch Zaliznyak , Ramanand Venkata , Henry Y. Lui
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： An integrated circuit includes a local clock network that is operable to provide a first clock signal and an interface circuit that is coupled to receive the first clock signal from the local clock network. The interface circuit is operable to generate a second clock signal based on the first clock signal. A clock line is coupled to the interface circuit. The clock line has a fixed length. The second clock signal is provided to a multiplexer circuit through the clock line. The multiplexer circuit provides a third clock signal based on the second clock signal. Another clock network is coupled to receive the third clock signal from the multiplexer circuit.
摘要翻译：集成电路包括可操作以提供第一时钟信号的本地时钟网络和耦合以从本地时钟网络接收第一时钟信号的接口电路。接口电路可操作以基于第一时钟信号产生第二时钟信号。时钟线耦合到接口电路。时钟线具有固定长度。第二时钟信号通过时钟线提供给多路复用器电路。多路复用器电路基于第二时钟信号提供第三时钟信号。另一个时钟网络被耦合以从多路复用器电路接收第三时钟信号。

8. 发明授权

US08571059B1 Apparatus and methods for serial interfaces with shared datapaths 有权
标题翻译：具有共享数据路径的串行接口的装置和方法
公开(公告)号：US08571059B1
公开(公告)日：2013-10-29
申请号：US13194536
申请日：2011-07-29
申请人： Arch Zaliznyak , Ramanand Venkata , Surinder Singh , Henry Y. Lui , Tim Tri Hoang , Sergey Shumarayev , Thungoc M. Tran
发明人： Arch Zaliznyak , Ramanand Venkata , Surinder Singh , Henry Y. Lui , Tim Tri Hoang , Sergey Shumarayev , Thungoc M. Tran
IPC分类号： H04J3/00
CPC分类号： G06F13/385
摘要： Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.
摘要翻译：公开了用于提供具有共享数据路径的串行接口的装置和方法。该装置和方法共享或重新使用来自多个低速数据路径的组件，以便有效地提供更高速度的数据通路。在一个实施例中，低速数据路径的物理编码子层电路也被较高速数据路径使用。在另一个实施例中，低速数据路径的物理介质访问电路也被高速数据路径使用。还公开了其它实施例，方面和特征。

9. 发明授权

US08994425B2 Techniques for aligning and reducing skew in serial data signals 有权
标题翻译：用于对齐和减少串行数据信号偏移的技术
公开(公告)号：US08994425B2
公开(公告)日：2015-03-31
申请号：US13566882
申请日：2012-08-03
申请人： Ramanand Venkata , Henry Lui , Arch Zaliznyak
发明人： Ramanand Venkata , Henry Lui , Arch Zaliznyak
IPC分类号： H03L7/00 , H03K5/1534
CPC分类号： H03K5/1534
摘要： A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.
摘要翻译：一个电路包括第一和第二对准器电路和一个去歪斜电路。第一对准器电路可操作以将第一输入串行数据信号与控制信号对准以产生第一对准的串行数据信号。第二对准器电路可操作以将第二输入串行数据信号与控制信号对准以产生第二对准的串行数据信号。去偏置电路可操作以减少第一和第二对准的串行数据信号之间的偏差，以产生第一和第二输出串行数据信号。

10. 发明授权

US07343569B1 Apparatus and method for reset distribution 有权
标题翻译：复位分配的装置和方法
公开(公告)号：US07343569B1
公开(公告)日：2008-03-11
申请号：US11351425
申请日：2006-02-10
申请人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
发明人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/66
摘要： A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.
摘要翻译：在支持多通道输入/输出协议的知识产权（IP）块中提供了容错，无毛刺的复位分配装置和方法。在复位模式期间，使用同步器创建更可预测的时序，流水线传播延迟，并允许在将复位信号路由到IP模块中的所有通道和通道内的RC时钟周期的RC引起的偏差。两个控制信号可从可编程逻辑资源核心电路获得，用于控制复位信号输入到IP模块。由于控制信号被设计为无毛刺，因此复位信号也无毛刺，从而防止IP块无意中转换或复位。

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