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    • 2. 发明授权
    • Signal detect for high-speed serial interface
    • 信号检测用于高速串行接口
    • US08290750B1
    • 2012-10-16
    • US13036437
    • 2011-02-28
    • Wilson WongAllen ChanSergey ShumarayevThungoc M. TranTim Tri HoangWeiqi Ding
    • Wilson WongAllen ChanSergey ShumarayevThungoc M. TranTim Tri HoangWeiqi Ding
    • H03F1/26
    • H03K5/19H03K19/1774H03K19/17744H03K19/1778
    • Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
    • 串行接口的信号检测电路对输入进行过采样,即每个时钟周期对输入进行多次采样,从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的,特别是在可编程器件中。 因此,在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题,大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的,允许用户设置用于信号检测的各种参数。
    • 6. 发明授权
    • Apparatus and methods for low-jitter transceiver clocking
    • 低抖动收发器时钟的装置和方法
    • US08406258B1
    • 2013-03-26
    • US12752984
    • 2010-04-01
    • Wilson WongTim Tri HoangThungoc M. TranSergey ShumarayevAllen Chan
    • Wilson WongTim Tri HoangThungoc M. TranSergey ShumarayevAllen Chan
    • H04J3/06
    • H03M9/00H03K19/1776H04J3/047H04J3/0685
    • One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.
    • 一个实施例涉及一种集成电路,其包括多个通信信道,每个信道中的时钟多路复用器,两个低抖动时钟发生器电路和时钟分配电路。 每个通道包括被布置为使用参考时钟信号传送串行数据流的电路,并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。 第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号,并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号 基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。 时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。 还公开了其它实施例和特征。
    • 8. 发明授权
    • Power supply filtering for programmable logic device having heterogeneous serial interface architecture
    • 具有异构串行接口架构的可编程逻辑器件的电源滤波
    • US07903679B1
    • 2011-03-08
    • US11622396
    • 2007-01-11
    • Sergey ShumarayevWilson WongThungoc M. TranTim Tri Hoang
    • Sergey ShumarayevWilson WongThungoc M. TranTim Tri Hoang
    • H04L12/56
    • H03K19/17744
    • In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.
    • 在具有多种不同类型的串行接口的可编程逻辑器件中,不同的电源滤波方案被应用于不同的接口。 对于以最低数据速率操作的接口,例如,可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。 对于以较高数据速率工作的接口,例如,也可以提供3 Gbps适度的封装内滤波,这可能包括功率岛解耦。 对于以更高的数据速率运行的接口,例如,也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。 对于以最高数据速率工作的接口,例如,可以提供10Gbps片上滤波,其可以包括一个或多个片上滤波或调节网络。 片上调节器可以可编程地旁路,允许用户权衡功能以节省功率。