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1. 发明授权

US06319783B1 Process to fabricate a novel source-drain extension 有权
标题翻译：制造新颖的源极 - 漏极扩展的过程
公开(公告)号：US06319783B1
公开(公告)日：2001-11-20
申请号：US09443425
申请日：1999-11-19
申请人： Ting Cheong Ang , Shyue Pong Quek , Jun Song , Xing Yu
发明人： Ting Cheong Ang , Shyue Pong Quek , Jun Song , Xing Yu
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.
摘要翻译：已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

2. 发明授权

US06300172B1 Method of field isolation in silicon-on-insulator technology 失效
标题翻译：硅绝缘体技术中的场隔离方法
公开(公告)号：US06300172B1
公开(公告)日：2001-10-09
申请号：US09409887
申请日：1999-10-01
申请人： Ting Cheong Ang , Shyue Pong Quek , Lap Chan , Sang Yee Loong
发明人： Ting Cheong Ang , Shyue Pong Quek , Lap Chan , Sang Yee Loong
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/76281
摘要： A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls. The gate oxide layer is removed between the gate conductor and the raised STIs, and outboard of the raised STIs. The source and drain are formed in the silicon-on-insulator layer adjacent the gate spacers. Silicide regions may then be formed on the source and drain.
摘要翻译：制造SOI晶体管器件的方法包括以下步骤。提供硅半导体结构。在硅半导体结构上形成氧化硅层。在氧化物层上形成绝缘体上硅层。将阱注入绝缘体上硅层中。栅氧化层生长在绝缘体上硅层上。在栅极氧化物层上沉积多晶硅层。对多晶硅层，栅极氧化物层和氧化硅层进行图案化和蚀刻以形成沟槽。沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的浅沟槽隔离区域（STI）。多晶硅层被图案化，并且非栅极部分去除与凸起的STI相邻的多晶硅，其在栅极导体和所述凸起的STI具有暴露的侧壁之间在凸起的STI之间形成栅极导体。栅极氧化物层在栅极导体和凸起的STI之间以及凸起的STIs的外侧被移除。源极和漏极形成在邻近栅极间隔物的绝缘体上硅层中。然后可以在源极和漏极上形成硅化物区域。

3. 发明授权

US6110787A Method for fabricating a MOS device 有权
标题翻译： MOS器件的制造方法
公开(公告)号：US6110787A
公开(公告)日：2000-08-29
申请号：US391886
申请日：1999-09-07
申请人： Lap Chan , Ting Cheong Ang , Shyue Pong Quek , Sang Yee Loong
发明人： Lap Chan , Ting Cheong Ang , Shyue Pong Quek , Sang Yee Loong
IPC分类号： H01L21/336 , H01L21/762 , H01L29/417 , H01L29/423
CPC分类号： H01L29/41775 , H01L21/76224 , H01L29/41783 , H01L29/6659 , H01L29/66628 , H01L29/78
摘要： A method of fabricating a MOS device having raised source/drain, raised isolation regions having isolation spacers, and a gate conductor having gate spacers is achieved. A layer of gate silicon oxide is grown over the surface of a semiconductor structure. A polysilicon layer is deposited overlying the gate silicon oxide layer. The polysilicon layer, gate silicon oxide layer and semiconductor structure are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised isolation regions. The remaining polysilicon layer is patterned to remove polysilicon adjacent the raised isolation regions forming a gate conductor between the raised isolation regions. The gate conductor and the raised isolation regions having exposed sidewalls. The gate oxide layer between the gate conductor and raised isolation regions is removed. Isolation spacers are formed on the exposed sidewalls of the raised isolation regions and gate spacers are formed on the exposed sidewalls of the gate conductor. A layer of silicon is deposited and patterned to form raised source and drain adjacent the gate spacers with source and drain being doped to form a MOS device.
摘要翻译：实现了具有升高的源极/漏极，具有隔离间隔物的升高的隔离区域以及具有栅极间隔物的栅极导体的MOS器件的制造方法。在半导体结构的表面上生长栅极氧化硅层。沉积覆盖栅氧化硅层的多晶硅层。对多晶硅层，栅极氧化硅层和半导体结构进行图案化和蚀刻以形成沟槽。沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的隔离区域。将剩余的多晶硅层图案化以去除在凸起的隔离区域之间形成栅极导体的凸起的隔离区域附近的多晶硅。栅极导体和凸起的隔离区域具有暴露的侧壁。去除栅极导体与升高隔离区之间的栅极氧化层。在凸起的隔离区域的暴露的侧壁上形成绝缘间隔物，并且栅极间隔物形成在栅极导体的暴露的侧壁上。沉积一层硅并图案化以形成与栅极间隔物相邻的凸起源极和漏极，源极和漏极被掺杂以形成MOS器件。

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