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1. 发明授权

US06300172B1 Method of field isolation in silicon-on-insulator technology 失效
标题翻译：硅绝缘体技术中的场隔离方法
公开(公告)号：US06300172B1
公开(公告)日：2001-10-09
申请号：US09409887
申请日：1999-10-01
申请人： Ting Cheong Ang , Shyue Pong Quek , Lap Chan , Sang Yee Loong
发明人： Ting Cheong Ang , Shyue Pong Quek , Lap Chan , Sang Yee Loong
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/76281
摘要： A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls. The gate oxide layer is removed between the gate conductor and the raised STIs, and outboard of the raised STIs. The source and drain are formed in the silicon-on-insulator layer adjacent the gate spacers. Silicide regions may then be formed on the source and drain.
摘要翻译：制造SOI晶体管器件的方法包括以下步骤。提供硅半导体结构。在硅半导体结构上形成氧化硅层。在氧化物层上形成绝缘体上硅层。将阱注入绝缘体上硅层中。栅氧化层生长在绝缘体上硅层上。在栅极氧化物层上沉积多晶硅层。对多晶硅层，栅极氧化物层和氧化硅层进行图案化和蚀刻以形成沟槽。沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的浅沟槽隔离区域（STI）。多晶硅层被图案化，并且非栅极部分去除与凸起的STI相邻的多晶硅，其在栅极导体和所述凸起的STI具有暴露的侧壁之间在凸起的STI之间形成栅极导体。栅极氧化物层在栅极导体和凸起的STI之间以及凸起的STIs的外侧被移除。源极和漏极形成在邻近栅极间隔物的绝缘体上硅层中。然后可以在源极和漏极上形成硅化物区域。

2. 发明授权

US6110787A Method for fabricating a MOS device 有权
标题翻译： MOS器件的制造方法
公开(公告)号：US6110787A
公开(公告)日：2000-08-29
申请号：US391886
申请日：1999-09-07
申请人： Lap Chan , Ting Cheong Ang , Shyue Pong Quek , Sang Yee Loong
发明人： Lap Chan , Ting Cheong Ang , Shyue Pong Quek , Sang Yee Loong
IPC分类号： H01L21/336 , H01L21/762 , H01L29/417 , H01L29/423
CPC分类号： H01L29/41775 , H01L21/76224 , H01L29/41783 , H01L29/6659 , H01L29/66628 , H01L29/78
摘要： A method of fabricating a MOS device having raised source/drain, raised isolation regions having isolation spacers, and a gate conductor having gate spacers is achieved. A layer of gate silicon oxide is grown over the surface of a semiconductor structure. A polysilicon layer is deposited overlying the gate silicon oxide layer. The polysilicon layer, gate silicon oxide layer and semiconductor structure are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised isolation regions. The remaining polysilicon layer is patterned to remove polysilicon adjacent the raised isolation regions forming a gate conductor between the raised isolation regions. The gate conductor and the raised isolation regions having exposed sidewalls. The gate oxide layer between the gate conductor and raised isolation regions is removed. Isolation spacers are formed on the exposed sidewalls of the raised isolation regions and gate spacers are formed on the exposed sidewalls of the gate conductor. A layer of silicon is deposited and patterned to form raised source and drain adjacent the gate spacers with source and drain being doped to form a MOS device.
摘要翻译：实现了具有升高的源极/漏极，具有隔离间隔物的升高的隔离区域以及具有栅极间隔物的栅极导体的MOS器件的制造方法。在半导体结构的表面上生长栅极氧化硅层。沉积覆盖栅氧化硅层的多晶硅层。对多晶硅层，栅极氧化硅层和半导体结构进行图案化和蚀刻以形成沟槽。沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的隔离区域。将剩余的多晶硅层图案化以去除在凸起的隔离区域之间形成栅极导体的凸起的隔离区域附近的多晶硅。栅极导体和凸起的隔离区域具有暴露的侧壁。去除栅极导体与升高隔离区之间的栅极氧化层。在凸起的隔离区域的暴露的侧壁上形成绝缘间隔物，并且栅极间隔物形成在栅极导体的暴露的侧壁上。沉积一层硅并图案化以形成与栅极间隔物相邻的凸起源极和漏极，源极和漏极被掺杂以形成MOS器件。

3. 发明授权

US06252290B1 Method to form, and structure of, a dual damascene interconnect device 有权
标题翻译：双镶嵌互连装置的形成和结构的方法
公开(公告)号：US06252290B1
公开(公告)日：2001-06-26
申请号：US09425903
申请日：1999-10-25
申请人： Shyue Fong Quek , Ting Cheong Ang , Lap Chan , Sang Yee Loong
发明人： Shyue Fong Quek , Ting Cheong Ang , Lap Chan , Sang Yee Loong
IPC分类号： H01L2900
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76835 , H01L2221/1026
摘要： A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack. The above steps are repeated n-1 times to form n-1 more dual damascene interconnects over the first level dual damascene interconnect where n is the number of interconnect levels desired. A passivation layer is deposited and patterned over the nth metal dual damascene interconnect layer to form openings in the passivation layer. The n number of via photo sensitive dielectric and trench photo sensitive dielectric layers are stripped and removed beneath the passivation layer openings and between the plurality of dual damascene structures wherein the portion of the via photo sensitive dielectric underneath the horizontal metal lines of the stripped trench photo sensitive dielectric layers remains.
摘要翻译：一种在半导体器件中制造双镶嵌互连结构的方法，包括以下步骤。通过光敏电介质层的第一级沉积并暴露在半导体结构上。第一级沟槽光电介质层被沉积并暴露在第一通孔光敏介电层上。通过光敏电介质和沟槽光敏电介质层曝光的第一级被图案化和蚀刻以形成第一级双镶嵌开口。第一级双镶嵌开口包括集成的第一级通孔和金属线开口。第一级金属层沉积在第一级沟槽光敏介电层上，填充第一级双镶嵌开口。第一级金属层被平坦化以形成具有第一级水平金属线和第一级垂直通孔叠层的至少一个第一级双镶嵌互连。上述步骤重复n-1次，以在第一级双镶嵌互连上形成n-1个双镶嵌互连，其中n是所需的互连级数。在第n个金属双镶嵌互连层上沉积并图案化钝化层，以在钝化层中形成开口。在钝化层开口之下和多个双镶嵌结构之间剥离并除去n个通孔光敏电介质层和沟槽光敏介电层，其中通过光敏电介质的部分在剥离的沟槽照片的水平金属线下方保持敏感的电介质层。

4. 发明授权

US06492242B1 Method of forming of high K metallic dielectric layer 失效
标题翻译：形成高K金属介电层的方法
公开(公告)号：US06492242B1
公开(公告)日：2002-12-10
申请号：US09609447
申请日：2000-07-03
申请人： Alex See , Cher Liang Randall Cha , Shyuz Fong Quek , Ting Cheong Ang , Wye Boon Loh , Sang Yee Loong , Jun Song , Chua Chee Tee
发明人： Alex See , Cher Liang Randall Cha , Shyuz Fong Quek , Ting Cheong Ang , Wye Boon Loh , Sang Yee Loong , Jun Song , Chua Chee Tee
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/31683
摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.
摘要翻译：在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化，已经开发该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度。第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域，通过覆盖光刻板中的透明区域。该过程还导致在下面的金属层的顶部上形成高K层。

5. 发明授权

US06258677B1 Method of fabricating wedge isolation transistors 失效
标题翻译：楔形隔离晶体管的制造方法
公开(公告)号：US06258677B1
公开(公告)日：2001-07-10
申请号：US09409875
申请日：1999-10-01
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L21/76264 , H01L21/76278 , H01L21/76283 , H01L21/823878 , H01L29/41783 , H01L29/66545 , H01L29/66628 , H01L29/66651
摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.
摘要翻译：一种制造晶体管的方法，包括以下步骤。提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。在活性区域上生长外延硅以形成SEG区域。在SEG区域上形成一个虚拟门。凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。去除虚拟栅极，暴露凸起的外延硅层的内侧壁。在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间。在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间形成栅极导体。去除侧壁间隔物。不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

6. 发明授权

US06248618B1 Method of fabrication of dual gate oxides for CMOS devices 有权
标题翻译：制造CMOS器件双栅氧化物的方法
公开(公告)号：US06248618B1
公开(公告)日：2001-06-19
申请号：US09415246
申请日：1999-10-12
申请人： Shyue Fong Quek , Ting Cheong Ang , Puay Ing Ong , Sang Yee Loong
发明人： Shyue Fong Quek , Ting Cheong Ang , Puay Ing Ong , Sang Yee Loong
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , Y10S438/981
摘要： A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the first active area by UV oxidation to form a first gate oxide layer having a first predetermined thickness. The first and second active areas are then simultaneously oxidized whereby the first predetermined thickness of the first gate oxide layer is increased to a second predetermined thickness and a second gate oxide layer having a predetermined thickness is formed in the second active area. The second predetermined thickness of the first oxide layer in the first active area is greater than the predetermined thickness of the second oxide layer in the second active area.
摘要翻译：一种形成厚薄的栅极氧化物的方法，包括以下步骤。提供具有由浅隔离沟槽区域隔开的第一和第二有源区的硅半导体衬底。通过UV氧化在第一有源区上选择性地形成氧化物生长，以形成具有第一预定厚度的第一栅氧化层。然后，第一和第二有源区域被同时氧化，由此第一栅极氧化物层的第一预定厚度增加到第二预定厚度，并且在第二有源区域中形成具有预定厚度的第二栅极氧化物层。第一有源区中的第一氧化物层的第二预定厚度大于第二有源区中第二氧化物层的预定厚度。

7. 发明授权

US06611024B2 Method of forming PID protection diode for SOI wafer 有权
公开(公告)号：US06611024B2
公开(公告)日：2003-08-26
申请号：US09946981
申请日：2001-09-06
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L2701
CPC分类号： H01L21/84 , H01L27/1203
摘要： An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

8. 发明授权

US06465296B1 Vertical source/drain contact semiconductor 有权
标题翻译：垂直源极/漏极接触半导体
公开(公告)号：US06465296B1
公开(公告)日：2002-10-15
申请号：US10167095
申请日：2002-06-10
申请人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
发明人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
IPC分类号： H01L218238
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L29/41733 , H01L29/458 , H01L29/66636 , H01L29/66825 , H01L29/78621
摘要： A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.
摘要翻译：提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。

9. 发明授权

US06406994B1 Triple-layered low dielectric constant dielectric dual damascene approach 有权
标题翻译：三层低介电常数电介质双镶嵌方法
公开(公告)号：US06406994B1
公开(公告)日：2002-06-18
申请号：US09726657
申请日：2000-11-30
申请人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
发明人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
IPC分类号： H01L2144
CPC分类号： B41M5/5254 , B41M5/508 , B41M5/5218 , B41M5/5272 , Y10T428/24802
摘要： A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.
摘要翻译：描述了三层低介电常数材料双镶嵌金属化工艺。金属线被覆盖在半导体衬底上的绝缘层所覆盖。第一类型的第一介电层沉积在绝缘层上。第二类型的第二介电层沉积在第一介电层上。通孔图案被蚀刻到第二介电层中。此后，第一类型的第三电介质层沉积在图案化的第二介电层上。同时，沟槽图案被蚀刻到第三介电层中，并且通孔图案被蚀刻到第一介电层中，以在集成电路器件的制造中完成双镶嵌开口的形成。如果第一种类型是低介电常数有机材料，则第二种类型将是低介电常数无机材料。如果第一种类型是低介电常数无机材料，则第二类型将是低介电常数有机材料。

10. 发明授权

US06787422B2 Method of body contact for SOI mosfet 有权
标题翻译： SOI mosfet的身体接触方法
公开(公告)号：US06787422B2
公开(公告)日：2004-09-07
申请号：US09755572
申请日：2001-01-08
申请人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
发明人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.
摘要翻译：描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。第一和第二沟槽填充有绝缘层。栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。沉积覆盖栅电极的层间电介质层。第一触点通过层间介质层开放到下面的源极和漏极区域。在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

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