专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07702972B2 Method and apparatus for SRAM macro sparing in computer chips 有权
标题翻译：用于计算机芯片中SRAM宏节省的方法和装置
公开(公告)号：US07702972B2
公开(公告)日：2010-04-20
申请号：US11874282
申请日：2007-10-18
申请人： Timothy Carl Bronson , Garrett Drapala , Hieu Trong Huynh , Patrick James Meaney
发明人： Timothy Carl Bronson , Garrett Drapala , Hieu Trong Huynh , Patrick James Meaney
IPC分类号： G11C29/00
CPC分类号： G11C29/846 , G11C11/41 , G11C29/814 , G11C29/816
摘要： SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.
摘要翻译：尽管丢失了一个或多个SRAM宏，但SRAM宏节省可以实现全芯片功能。受保护组内任何单个宏的控件和数据流都可用于该组的备用或备用。这允许关闭SRAM故障或故障，并由备用宏替换，大大提高制造成品率和减少现场更换率。受保护组越大，产量类似提高所需的备件数量就越少，而使所有控制和数据流可用于备件的任务越困难。在计划的IBM Z6计算机的2级缓存芯片的情况下，每组有4个受保护组，192个SRAM宏。每个受保护的组被替换为额外的2个备用SRAM宏，以及备用控制和数据流，允许备用替换任何192个受保护的SRAM宏。

2. 发明申请

US20090106607A1 Method and Apparatus for SRAM Macro Sparing in Computer Chips 有权
标题翻译：计算机芯片中SRAM宏节省的方法和设备
公开(公告)号：US20090106607A1
公开(公告)日：2009-04-23
申请号：US11874282
申请日：2007-10-18
申请人： Timothy Carl Bronson , Garrett Drapala , Hieu Trong Huynh , Patrick James Meaney
发明人： Timothy Carl Bronson , Garrett Drapala , Hieu Trong Huynh , Patrick James Meaney
IPC分类号： G06F11/20
CPC分类号： G11C29/846 , G11C11/41 , G11C29/814 , G11C29/816
摘要： SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.
摘要翻译：尽管丢失了一个或多个SRAM宏，但SRAM宏节省可以实现全芯片功能。受保护组内任何单个宏的控件和数据流都可用于该组的备用或备用。这允许关闭SRAM故障或故障，并由备用宏替换，大大提高制造成品率和减少现场更换率。受保护组越大，产量类似提高所需的备件数量就越少，而使所有控制和数据流可用于备件的任务越困难。在计划的IBM Z6计算机的2级缓存芯片的情况下，每组有4个受保护组，192个SRAM宏。每个受保护的组被替换为额外的2个备用SRAM宏，以及备用控制和数据流，允许备用替换任何192个受保护的SRAM宏。

3. 发明授权

US06621353B2 Phase locked loop reconfiguration 有权
标题翻译：锁相环重新配置
公开(公告)号：US06621353B2
公开(公告)日：2003-09-16
申请号：US10053033
申请日：2001-11-07
申请人： Timothy Carl Bronson , David Andrew Thorndike
发明人： Timothy Carl Bronson , David Andrew Thorndike
IPC分类号： H03L700
CPC分类号： H03L7/06
摘要： Dedicated registers sequenced by a state machine capture phase locked loop reconfiguration values or parameters and load them into a reconfigurable phase locked loop in order to achieve rapid and reliable reconfiguration with high immunity from clock glitches and jitter as the phase locked loop goes in and out of lock. In the preferred environment of a digital bus, reconfiguration values or parameters can be supplied through a normal bus transaction and no dedicated connections are required for phase locked loop reconfiguration.
摘要翻译：专用寄存器由状态机排序捕获锁相环重配置值或参数，并将其加载到可重配置锁相环中，以便实现快速可靠的重配置，具有高抗时钟脉冲和抖动的抗扰度，因为锁相环进出锁。在数字总线的优选环境中，可以通过正常总线事务提供重新配置值或参数，并且不需要用于锁相环重新配置的专用连接。

4. 发明授权

US06920519B1 System and method for supporting access to multiple I/O hub nodes in a host bridge 有权
标题翻译：用于支持访问主桥中的多个I / O中枢节点的系统和方法
公开(公告)号：US06920519B1
公开(公告)日：2005-07-19
申请号：US09569059
申请日：2000-05-10
申请人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda , Anthony J Bybell , Stefan Peter Jackowski , William Garrett Verdoorn, Jr. , Phillip G Williams
发明人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda , Anthony J Bybell , Stefan Peter Jackowski , William Garrett Verdoorn, Jr. , Phillip G Williams
IPC分类号： G06F3/00 , G06F12/00 , G06F12/02 , G06F12/10 , G06F13/36 , G06F13/40
CPC分类号： G06F13/404 , G06F12/0284 , G06F12/1027 , G06F2212/682
摘要： Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.
摘要翻译：将数据动态路由到多个处理器复合体。 PCI地址空间被细分为多个处理器复合体。每个处理器复合体处的转换表条目确定哪个处理器复合体将接收DMA传输，从而在访问另一个I / O集线器节点处的转换表条目时，使DMA数据能够路由到一个I / O集线器节点。此外，中断请求可以被动态地路由到多个处理器复合体。

5. 发明授权

US06785759B1 System and method for sharing I/O address translation caching across multiple host bridges 失效
标题翻译：在多个主机桥上共享I / O地址转换缓存的系统和方法
公开(公告)号：US06785759B1
公开(公告)日：2004-08-31
申请号：US09569574
申请日：2000-05-10
申请人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda
发明人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda
IPC分类号： G06F100
CPC分类号： G06F12/0292 , G06F12/1027 , G06F2212/303 , G06F2213/0038
摘要： A processor system includes an I/O bus to host bridge in which I/O address translation elements are shared across multiple I/O bus bridges. A TCE manager is provided for retaining in cache a TCE entry associated with a discarded channel for association with a new channel responsive to a subsequent read request for a memory page referenced by the TCE entry.
摘要翻译：处理器系统包括一个主机桥的I / O总线，其中I / O地址转换元件在多个I / O总线桥上共享。提供TCE管理器，用于在缓存中保留与被丢弃的信道相关联的TTS条目，用于响应于对由TCE条目引用的存储器页面的后续读取请求与新信道相关联。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式