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1. 发明授权

US07702972B2 Method and apparatus for SRAM macro sparing in computer chips 有权
标题翻译：用于计算机芯片中SRAM宏节省的方法和装置
公开(公告)号：US07702972B2
公开(公告)日：2010-04-20
申请号：US11874282
申请日：2007-10-18
申请人： Timothy Carl Bronson , Garrett Drapala , Hieu Trong Huynh , Patrick James Meaney
发明人： Timothy Carl Bronson , Garrett Drapala , Hieu Trong Huynh , Patrick James Meaney
IPC分类号： G11C29/00
CPC分类号： G11C29/846 , G11C11/41 , G11C29/814 , G11C29/816
摘要： SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.
摘要翻译：尽管丢失了一个或多个SRAM宏，但SRAM宏节省可以实现全芯片功能。受保护组内任何单个宏的控件和数据流都可用于该组的备用或备用。这允许关闭SRAM故障或故障，并由备用宏替换，大大提高制造成品率和减少现场更换率。受保护组越大，产量类似提高所需的备件数量就越少，而使所有控制和数据流可用于备件的任务越困难。在计划的IBM Z6计算机的2级缓存芯片的情况下，每组有4个受保护组，192个SRAM宏。每个受保护的组被替换为额外的2个备用SRAM宏，以及备用控制和数据流，允许备用替换任何192个受保护的SRAM宏。

2. 发明申请

US20090106607A1 Method and Apparatus for SRAM Macro Sparing in Computer Chips 有权
标题翻译：计算机芯片中SRAM宏节省的方法和设备
公开(公告)号：US20090106607A1
公开(公告)日：2009-04-23
申请号：US11874282
申请日：2007-10-18
申请人： Timothy Carl Bronson , Garrett Drapala , Hieu Trong Huynh , Patrick James Meaney
发明人： Timothy Carl Bronson , Garrett Drapala , Hieu Trong Huynh , Patrick James Meaney
IPC分类号： G06F11/20
CPC分类号： G11C29/846 , G11C11/41 , G11C29/814 , G11C29/816
摘要： SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.
摘要翻译：尽管丢失了一个或多个SRAM宏，但SRAM宏节省可以实现全芯片功能。受保护组内任何单个宏的控件和数据流都可用于该组的备用或备用。这允许关闭SRAM故障或故障，并由备用宏替换，大大提高制造成品率和减少现场更换率。受保护组越大，产量类似提高所需的备件数量就越少，而使所有控制和数据流可用于备件的任务越困难。在计划的IBM Z6计算机的2级缓存芯片的情况下，每组有4个受保护组，192个SRAM宏。每个受保护的组被替换为额外的2个备用SRAM宏，以及备用控制和数据流，允许备用替换任何192个受保护的SRAM宏。

3. 发明授权

US07987400B2 Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy 有权
标题翻译：优化具有多层次结构的集成电路中的扫描链的方法
公开(公告)号：US07987400B2
公开(公告)日：2011-07-26
申请号：US12035500
申请日：2008-02-22
申请人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
发明人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318536
摘要： A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.
摘要翻译：一种用于优化集成电路中具有多层次层次结构的扫描链的方法，可以解决无限链和树桩，并分开所有其他链和树桩。通过将链包围的区域和残端的起始点和终点分成由多个网格框组成的网格，并且将网格框确定为网格框连接路由以访问所有网格框，来优化无限链和树桩的起始点和终点之间的网格框通过运行路由算法的计算机。优化的所有其他链和树桩被随机地分配给一个树桩，一个可以通过该树桩物理达到的链，并根据附加链中的锁存数，其物理位置和锁存数量向该残基添加一个附加链已分配

4. 发明授权

US6055660A Method for identifying SMP bus transfer errors 失效
标题翻译：识别SMP总线传输错误的方法
公开(公告)号：US6055660A
公开(公告)日：2000-04-25
申请号：US942817
申请日：1997-10-02
申请人： Patrick James Meaney
发明人： Patrick James Meaney
IPC分类号： G06F11/267 , G06F11/00
CPC分类号： G06F11/221
摘要： In an SMP computer system where data is partitioned across one or more chips a circuit and method permits detecting errors across chip boundaries due to a control error even though the ECC is not bad. A Multiple-input Shift-Register (MISR) on each bus is used to collect a dynamic signature representing all the critical buses on each chip that need to be compared. The MISR state combines present and previous states of these buses, so the MISR will be different if one or more bus controls break. Since an N-bit MISR shifts, comparing a single bit of the MISR each cycle guarantees detection within N cycles of a problem. The method of identifying errors includes accumulating bus signature information which is a function of current and previous values of an input bus and then comparing portions of the signatures of two or more input bus structures to determine sync of buses. Part of the signature is wrapped around into the signature to cause past information to be maintained indefinitely. Additional logic is introduced, including mask logic, programmable feedback, and counters along with a method of isolating defects using these features.
摘要翻译：在通过一个或多个芯片分割数据的SMP计算机系统中，由于控制错误，电路和方法允许跨芯片边界检测错误，即使ECC不坏。每个总线上的多输入移位寄存器（MISR）用于收集表示需要进行比较的每个芯片上所有关键总线的动态签名。 MISR状态结合了这些总线的现状和以前的状态，因此如果一个或多个总线控制断开，MISR将是不同的。由于N位MISR移位，所以比较每个周期的MISR的单个位保证在N个周期内的问题的检测。识别错误的方法包括：累积作为输入总线的当前值和先前值的函数的总线签名信息，然后比较两个或多个输入总线结构的签名的部分，以确定总线的同步。签名的一部分被包裹在签名中，以使得过去的信息被无限期地维护。引入了附加逻辑，包括掩模逻辑，可编程反馈和计数器以及使用这些特征隔离缺陷的方法。

5. 发明授权

US5784383A Apparatus for identifying SMP bus transfer errors 失效
标题翻译：用于识别SMP总线传输错误的装置
公开(公告)号：US5784383A
公开(公告)日：1998-07-21
申请号：US942816
申请日：1997-10-02
申请人： Patrick James Meaney
发明人： Patrick James Meaney
IPC分类号： G06F11/16 , G06F11/00
CPC分类号： G06F11/1625 , G06F2201/83
摘要： In an SMP computer system where data is partitioned across one or more chips a circuit and method permits detecting errors across chip boundaries due to a control error even though the ECC is not bad. A Multiple-input Shift-Register (MISR) on each bus is used to collect a dynamic signature representing all the critical buses on each chip that need to be compared. The MISR state combines present and previous states of these buses, so the MISR will be different if one or more bus controls break. Since an N-bit MISR shifts, comparing a single bit of the MISR each cycle guarantees detection within N cycles of a problem. The method for identifying errors includes accumulating bus signature information which is a function of current and previous values of an input bus and then comparing portions of the signatures of two or more input bus structures to determine sync of buses. Part of the signature is wrapped around into the signature to cause past information to be maintained indefinitely. Additional logic is introduced, including mask logic, programmable feedback, and counters along with a method for isolating defects using these features.
摘要翻译：在通过一个或多个芯片分割数据的SMP计算机系统中，由于控制错误，电路和方法允许跨芯片边界检测错误，即使ECC不坏。每个总线上的多输入移位寄存器（MISR）用于收集表示需要进行比较的每个芯片上所有关键总线的动态签名。 MISR状态结合了这些总线的现状和以前的状态，因此如果一个或多个总线控制断开，MISR将是不同的。由于N位MISR移位，所以比较每个周期的MISR的单个位保证在N个周期内的问题的检测。用于识别错误的方法包括累积作为输入总线的当前值和先前值的函数的总线签名信息，然后比较两个或更多个输入总线结构的签名的部分以确定总线的同步。签名的一部分被包裹在签名中，以使得过去的信息被无限期地维护。引入了附加逻辑，包括掩模逻辑，可编程反馈和计数器以及使用这些特征来隔离缺陷的方法。

6. 发明授权

US5774481A Reduced gate error detection and correction circuit 失效
标题翻译：减少门误差检测和校正电路
公开(公告)号：US5774481A
公开(公告)日：1998-06-30
申请号：US414064
申请日：1995-03-31
申请人： Patrick James Meaney , Chin-Long Chen
发明人： Patrick James Meaney , Chin-Long Chen
IPC分类号： G06F11/10 , H03M13/13 , H03M13/00
CPC分类号： G06F11/1012 , H03M13/13
摘要： Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit position. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.
摘要翻译：错误检测和校正电路，经过优化，可减少校正单个错误所需的时间并检测是否存在不可校正的错误，使用优化的H-Matrix并提供减少的逻辑电路。可纠正的误差综合征被定义为包括奇数个，并且当检测到偶数个错误时，不可校正错误检测电路产生不可校正错误指示。可校正错误综合征被定义为在一组相应位位置中的每一个中具有预定义的1和0的组合，以及在其它位位置中具有不同的1和0的组合。仅包括零的错误综合征被指定为无错误状态的指示。提供逻辑电路，其实现具有减少的逻辑门集合的错误检测和校正电路。

7. 发明授权

US07979838B2 Method of automating creation of a clock control distribution network in an integrated circuit floorplan 有权
标题翻译：在集成电路平面图中自动创建时钟控制分配网络的方法
公开(公告)号：US07979838B2
公开(公告)日：2011-07-12
申请号：US12032517
申请日：2008-02-15
申请人： Christopher J. Berry , Jose Luis Pontes Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, Jr.
发明人： Christopher J. Berry , Jose Luis Pontes Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.
摘要翻译：在集成芯片设计中布置时钟控制分配网络的平面图的过程被简化，并且提高了创建分段网络的效率。在Cadence Viewer中查看芯片平面图的图片时，不是在HDL中手动创建分段网络，也可以将其作为网络描述表，在Cadence环境中运行的自动化方法使用算法方法来最大限度地利用分段锁存器，消除不必要的电源和区域使用。通过使用算法到达的分段解决方案直接更新物理布局来最大化效率。

8. 发明申请

US20090210843A1 Method of Automating Creation of a Clock Control Distribution Network in an Integrated Circuit Floorplan 有权
标题翻译：在集成电路平面图中自动创建时钟控制分配网络的方法
公开(公告)号：US20090210843A1
公开(公告)日：2009-08-20
申请号：US12032517
申请日：2008-02-15
申请人： Christopher J. Berry , Jose Luis Ponters Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, JR.
发明人： Christopher J. Berry , Jose Luis Ponters Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, JR.
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.
摘要翻译：在集成芯片设计中布置时钟控制分配网络的平面图的过程被简化，并且提高了创建分段网络的效率。在Cadence Viewer中查看芯片平面图的图片时，不是在HDL中手动创建分段网络，也可以将其作为网络描述表，在Cadence环境中运行的自动化方法使用算法方法来最大限度地提高利用率分段锁存器，消除不必要的电源和区域使用。通过使用算法到达的分段解决方案直接更新物理布局来最大化效率。

9. 发明授权

US6163857A Computer system UE recovery logic 失效
标题翻译：计算机系统UE恢复逻辑
公开(公告)号：US6163857A
公开(公告)日：2000-12-19
申请号：US70389
申请日：1998-04-30
申请人： Patrick James Meaney , Pak-kin Mak , William Wu Shen , Gary Eugene Strait
发明人： Patrick James Meaney , Pak-kin Mak , William Wu Shen , Gary Eugene Strait
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/1064
摘要： A computer system having central processors (CPs), an associated L2 cache, and processor memory arrays (PMAs), is provided with store logic and and fetch logic used to detect and correct data errors and to write the resulting data the associated cache. The store logic and and fetch logic blocks UEs from the cache for CP stores, for PMA (mainstore) fetches/loads, and for cache-to-cache loads, and with uncorrectable error recovery cache fetch and store logic injects `Special UEs` into the cache when loads cannot be blocked and abends CP jobs for UEs during CP stores, for UEs from PMA, for UEs from remote cache, and for UEs from local cache. This logic performs reconfiguring of memory when UEs are detected in memory and also blocks cache data propagation on UEs for CP fetches, for Cache-to-Cache transfer if data is unchanged, and for PMA castouts if data is unchanged, as well as forces castouts when UEs appear on changed cache data; injects `Special UEs` for UEs detected on changed cache data; invalidates the cache when UEs are detected in the local cache; and only deletes cache entries that have repeated failures.
摘要翻译：具有中央处理器（CP），相关联的L2高速缓存和处理器存储器阵列（PMA）的计算机系统被提供有用于检测和校正数据错误并且将结果数据写入相关联的高速缓存的存储逻辑和提取逻辑。存储逻辑和提取逻辑阻止来自用于CP的高速缓存的UE存储用于PMA（主仓）提取/加载以及用于高速缓存到高速缓存加载的UE，并且具有不可校正的错误恢复高速缓存提取和存储逻辑将“特殊UE”注入在CP存储期间，对于来自PMA的UE，对于来自远程高速缓存的UE以及用于来自本地高速缓存的UE，不能阻止加载时的缓存并退出用于UE的CP作业。当在存储器中检测到UE时，该逻辑执行存储器的重新配置，并且还阻止用于CP提取的UE上的高速缓存数据传播，如果数据不变，则用于缓存到缓存传输，以及如果数据不变，则阻止PMA丢弃，以及强制转移当UE出现在更改的缓存数据上时; 针对在更改的缓存数据上检测到的UE注入“特殊UE”; 在本地高速缓存中检测到UE时使高速缓存失效; 并且只删除重复出现故障的缓存条目。

10. 发明授权

US6038626A Method for controlling data transfers and routing 失效
标题翻译：控制数据传输和路由的方法
公开(公告)号：US6038626A
公开(公告)日：2000-03-14
申请号：US42971
申请日：1998-03-17
申请人： Patrick James Meaney , Frank Malgioglio
发明人： Patrick James Meaney , Frank Malgioglio
IPC分类号： G06F13/00 , G06F13/40 , G06F11/00 , G06F17/60
CPC分类号： G06F13/4004
摘要： A scalable selector and method for a data processing system provides a multiple-bit, multiple bus selector logic for controling data routing and allowing dataflow to be connected and reconnected without change to control logic. The scalable selector logic includes a data selector controlled by the input controls as could accommodate controls from the Prior Art, as well providing an additional Orthogonality Checker to monitor for the condition where more than one control signal is active, and additional Data Valid logic to determine whether any of the input data buses has been selected to the output. The scalable selectors can be used in a switching network where these additional outputs operate as network controls allowing for the selection of buses in a switch network with orthogonality checking and data valid generation. The selectors also allow for swapping of data ports for timing and function sharing without impacting existing external control logic.
摘要翻译：用于数据处理系统的可扩展选择器和方法提供了一种多位多总线选择器逻辑，用于控制数据路由并允许数据流被连接和重新连接，而不改变为控制逻辑。可扩展选择器逻辑包括由输入控制器控制的数据选择器，其可以适应现有技术的控制，并且还提供附加的正交检查器来监视多于一个控制信号有效的情况，以及另外的数据有效逻辑来确定是否已将任何输入数据总线选择到输出。可扩展选择器可用于交换网络，其中这些附加输出作为网络控制，允许在具有正交性检查和数据有效生成的交换机网络中选择总线。选择器还允许数据端口交换用于定时和功能共享，而不会影响现有的外部控制逻辑。

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