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1. 发明授权

US6115795A Method and apparatus for configurable multiple level cache with coherency in a multiprocessor system 失效
标题翻译：在多处理器系统中具有一致性的可配置多级缓存的方法和装置
公开(公告)号：US6115795A
公开(公告)日：2000-09-05
申请号：US908140
申请日：1997-08-06
申请人： Glenn David Gilda , Steven Lee Gregor
发明人： Glenn David Gilda , Steven Lee Gregor
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0835
摘要： A coherency controller for configurable caches. A base microprocessor design accommodates system configurations both with and without L2 cache tag and data arrays installed. Second level cache control logic exists within the microprocessor chip, and when the external second level cache tag and data arrays are removed their inputs to the microprocessor are tied to an inactive state. A configuration switch is set in the second level cache controller that causes snoop requests from a system bus to get reflected onto a first level cache snooping path. The first level cache status is then fed back to the second level cache controller, in a manner consistent with the timing required for support of a second level cache search, and fed into the second level cache status signal generation logic, effectively making the second level cache controller believe that the second level cache still exists for snooping. All other actions remain the same in the second level cache controller providing an effective and simple method for supporting snooping bus protocols. A result is that now every bus request snoops the first level cache without knowledge of presence of an L2 cache. This environment is provided to support entry level single processor configurations where the snooping requests only amount to input/output traffic.
摘要翻译：用于可配置缓存的一致性控制器。基本的微处理器设计适用于具有和不具有L2缓存标签和数据阵列的系统配置。二级缓存控制逻辑存在于微处理器芯片内，当外部二级高速缓存标签和数据阵列被移除时，它们对微处理器的输入被连接到非活动状态。在第二级高速缓存控制器中设置配置开关，导致来自系统总线的窥探请求被反映到第一级高速缓存窥探路径上。然后以与支持第二级高速缓存搜索所需的定时一致的方式将第一级高速缓存状态反馈到第二级高速缓存控制器，并且馈送到第二级高速缓存状态信号生成逻辑，有效地使第二级高速缓存状态信号生成逻辑缓存控制器认为第二级缓存仍然存在于窥探中。所有其他动作在二级缓存控制器中保持不变，提供了一种有效和简单的支持窥探总线协议的方法。结果是现在每个总线请求都窥探第一级缓存，而不知道存在二级缓存。提供此环境以支持入门级单处理器配置，其中窥探请求仅等于输入/输出流量。

2. 发明授权

US06490660B1 Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor system 失效
标题翻译：在多处理器系统中具有一致性的可配置多级缓存的方法和装置
公开(公告)号：US06490660B1
公开(公告)日：2002-12-03
申请号：US09610200
申请日：2000-07-01
申请人： Glenn David Gilda , Steven Lee Gregor
发明人： Glenn David Gilda , Steven Lee Gregor
IPC分类号： G06F1208
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0835
摘要： A coherency controller for configurable caches. A base microprocessor design accommodates system configurations both with and without L2 cache tag and data arrays installed. Second level cache control logic exists within the microprocessor chip, and when the external second level cache tag and data arrays are removed their inputs to the microprocessor are tied to an inactive state. A configuration switch is set in the second level cache controller that causes snoop requests from a system bus to get reflected onto a first level cache snooping path. The first level cache status is then fed back to the second level cache controller, in a manner consistent with the timing required for support of a second level cache search, and fed into the second level cache status signal generation logic, effectively making the second level cache controller believe that the second level cache still exists for snooping. All other actions remain the same in the second level cache controller providing an effective and simple method for supporting snooping bus protocols. A result is that now every bus request snoops the first level cache without knowledge of presence of an L2 cache. This environment is provided to support entry level single processor configurations where the snooping requests only amount to input/output traffic.
摘要翻译：用于可配置缓存的一致性控制器。基本的微处理器设计适用于具有和不具有L2缓存标签和数据阵列的系统配置。二级缓存控制逻辑存在于微处理器芯片内，当外部二级高速缓存标签和数据阵列被移除时，它们对微处理器的输入被连接到非活动状态。在第二级高速缓存控制器中设置配置开关，导致来自系统总线的窥探请求被反映到第一级高速缓存窥探路径上。然后以与支持第二级高速缓存搜索所需的定时一致的方式将第一级高速缓存状态反馈到第二级高速缓存控制器，并且馈送到第二级高速缓存状态信号生成逻辑，有效地使第二级高速缓存状态信号生成逻辑缓存控制器认为第二级缓存仍然存在于窥探中。所有其他动作在二级缓存控制器中保持不变，提供了一种有效和简单的支持窥探总线协议的方法。结果是现在每个总线请求都窥探第一级缓存，而不知道存在二级缓存。提供此环境以支持入门级单处理器配置，其中窥探请求仅等于输入/输出流量。

3. 发明授权

US06438657B1 Pipelined snooping of multiple L1 cache lines 失效
标题翻译：多条L1高速缓存行的流水线窥探
公开(公告)号：US06438657B1
公开(公告)日：2002-08-20
申请号：US09399286
申请日：1999-09-17
申请人： Glenn David Gilda
发明人： Glenn David Gilda
IPC分类号： G06F1208
CPC分类号： G06F12/0811 , G06F12/0831
摘要： A cache system is provided for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A two level cache subsystem including an L1 cache and an L2 cache is provided. A cache directory is accessed for a second snoop request while a directory access from a first snoop request is being evaluated. During a REQUEST stage, a directory access snoop to the directory of the L1 cache is requested; and responsive thereto, during a SNOOP stage, the directory is accessed; during an ACCESS stage, the cache arrays are accessed while processing results from the SNOOP stage. If multiple data transfers are required out of the L1 cache, a pipeline hold is issued to the REQUEST and SNOOP stages, and the ACCESS stage is repeated. During a FLUSH stage, cache data read from the L1 cache during the ACCESS stage is sent to the L2 cache.
摘要翻译：提供了缓存系统，用于访问集合关联缓存，而不增加关键路径延迟，以减少高速缓存访问的延迟损失，减少侦听占线时间，以及响应MRU未命中和高速缓存未命中。提供了包括L1高速缓存和L2高速缓存的两级缓存子系统。对第二个窥探请求进行缓存目录访问，同时正在评估来自第一个窥探请求的目录访问。在REQUEST阶段，请求目录访问窥探到L1缓存的目录; 并且响应于此，在SNOOP阶段期间，访问该目录; 在ACCESS阶段期间，在处理来自SNOOP阶段的结果时访问高速缓存阵列。如果在L1高速缓存中需要多个数据传输，则向REQUEST和SNOOP阶段发出流水线保持，并重复ACCESS阶段。在FLUSH阶段，在ACCESS阶段从L1高速缓存读取的缓存数据被发送到L2高速缓存。

4. 发明授权

US6065101A Pipelined snooping of multiple L1 cache lines 失效
公开(公告)号：US6065101A
公开(公告)日：2000-05-16
申请号：US873991
申请日：1997-06-12
申请人： Glenn David Gilda
发明人： Glenn David Gilda
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0831
摘要： A cache system is provided for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A two level cache subsystem including an L1 cache and an L2 cache is provided. A cache directory is accessed for a second snoop request while a directory access from a first snoop request is being evaluated. During a REQUEST stage, a directory access snoop to the directory of the L1 cache is requested; and responsive thereto, during a SNOOP stage, the directory is accessed; during an ACCESS stage, the cache arrays are accessed while processing results from the SNOOP stage. If multiple data transfers are required out of the L1 cache, a pipeline hold is issued to the REQUEST and SNOOP stages, and the ACCESS stage is repeated. During a FLUSH stage, cache data read from the L1 cache during the ACCESS stage is sent to the L2 cache.

5. 发明授权

US06920519B1 System and method for supporting access to multiple I/O hub nodes in a host bridge 有权
标题翻译：用于支持访问主桥中的多个I / O中枢节点的系统和方法
公开(公告)号：US06920519B1
公开(公告)日：2005-07-19
申请号：US09569059
申请日：2000-05-10
申请人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda , Anthony J Bybell , Stefan Peter Jackowski , William Garrett Verdoorn, Jr. , Phillip G Williams
发明人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda , Anthony J Bybell , Stefan Peter Jackowski , William Garrett Verdoorn, Jr. , Phillip G Williams
IPC分类号： G06F3/00 , G06F12/00 , G06F12/02 , G06F12/10 , G06F13/36 , G06F13/40
CPC分类号： G06F13/404 , G06F12/0284 , G06F12/1027 , G06F2212/682
摘要： Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.
摘要翻译：将数据动态路由到多个处理器复合体。 PCI地址空间被细分为多个处理器复合体。每个处理器复合体处的转换表条目确定哪个处理器复合体将接收DMA传输，从而在访问另一个I / O集线器节点处的转换表条目时，使DMA数据能够路由到一个I / O集线器节点。此外，中断请求可以被动态地路由到多个处理器复合体。

6. 发明授权

US06785759B1 System and method for sharing I/O address translation caching across multiple host bridges 失效
标题翻译：在多个主机桥上共享I / O地址转换缓存的系统和方法
公开(公告)号：US06785759B1
公开(公告)日：2004-08-31
申请号：US09569574
申请日：2000-05-10
申请人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda
发明人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda
IPC分类号： G06F100
CPC分类号： G06F12/0292 , G06F12/1027 , G06F2212/303 , G06F2213/0038
摘要： A processor system includes an I/O bus to host bridge in which I/O address translation elements are shared across multiple I/O bus bridges. A TCE manager is provided for retaining in cache a TCE entry associated with a discarded channel for association with a new channel responsive to a subsequent read request for a memory page referenced by the TCE entry.
摘要翻译：处理器系统包括一个主机桥的I / O总线，其中I / O地址转换元件在多个I / O总线桥上共享。提供TCE管理器，用于在缓存中保留与被丢弃的信道相关联的TTS条目，用于响应于对由TCE条目引用的存储器页面的后续读取请求与新信道相关联。

7. 发明授权

US06138206A Data register for multicycle data cache read 失效
标题翻译：用于多周期数据高速缓存读取的数据寄存器
公开(公告)号：US06138206A
公开(公告)日：2000-10-24
申请号：US873962
申请日：1997-06-12
申请人： Michael Todd Fisher , Glenn David Gilda
发明人： Michael Todd Fisher , Glenn David Gilda
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses and for responding to slot MRU misses and cache misses. An N-way set associative cache is provided, each set of said cache including an SRAM array macro having a memory element, an internal SRAM data register, and a read enable signal line. Read enable is generated as the NOR of slot miss and cache miss signals, and the internal SRAM data register is responsive to the slot miss signal for registering data output during a first cycle for use in a next following cycle.
摘要翻译：高速缓存系统提供访问集合关联缓存，而不增加关键路径延迟，以减少高速缓存访问的延迟损失以及响应时隙MRU丢失和高速缓存未命中。提供N路组关联高速缓存，每组所述高速缓存包括具有存储元件的SRAM阵列宏，内部SRAM数据寄存器和读使能信号线。读取使能被生成为时隙未命中和高速缓存未命中信号的NOR，并且内部SRAM数据寄存器响应于槽缺失信号，用于在第一周期期间注册数据输出以用于下一个后续周期。

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