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1. 发明申请

US20110209011A1 METHOD FOR ERROR TEST, RECORDATION AND REPAIR 失效
标题翻译：错误测试，记录和修复方法
公开(公告)号：US20110209011A1
公开(公告)日：2011-08-25
申请号：US13098569
申请日：2011-05-02
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G06F11/20
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

2. 发明授权

US07941712B2 Method for error test, recordation and repair 有权
标题翻译：错误测试，记录和修复方法
公开(公告)号：US07941712B2
公开(公告)日：2011-05-10
申请号：US11714348
申请日：2007-03-06
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G11C29/00
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

3. 发明授权

US08499207B2 Memory devices and method for error test, recordation and repair 有权
标题翻译：内存设备和方法进行错误测试，记录和修复
公开(公告)号：US08499207B2
公开(公告)日：2013-07-30
申请号：US13559942
申请日：2012-07-27
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

4. 发明申请

US20120297257A1 MEMORY DEVICES AND METHOD FOR ERROR TEST, RECORDATION AND REPAIR 有权
标题翻译：用于错误测试，记录和修复的记忆装置和方法
公开(公告)号：US20120297257A1
公开(公告)日：2012-11-22
申请号：US13559942
申请日：2012-07-27
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G06F11/20
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

5. 发明授权

US08234527B2 Method for error test, recordation and repair 失效
标题翻译：错误测试，记录和修复方法
公开(公告)号：US08234527B2
公开(公告)日：2012-07-31
申请号：US13098569
申请日：2011-05-02
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

6. 发明授权

US07509543B2 Circuit and method for error test, recordation, and repair 失效
标题翻译：错误测试，记录和修复的电路和方法
公开(公告)号：US07509543B2
公开(公告)日：2009-03-24
申请号：US10464762
申请日：2003-06-17
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

7. 发明授权

US06918072B2 Circuit and method for time-efficient memory repair 失效
标题翻译：电路和时间效率记忆修复方法
公开(公告)号：US06918072B2
公开(公告)日：2005-07-12
申请号：US09864682
申请日：2001-05-24
申请人： Timothy B. Cowles , Christian N. Mohr
发明人： Timothy B. Cowles , Christian N. Mohr
IPC分类号： G01R31/28 , G11C11/401 , G11C11/413 , G11C16/02 , G11C29/00 , G11C29/12 , G11C29/44
CPC分类号： G11C29/72 , G11C29/44
摘要： Circuitry is provided to allow early switching of input signals from a first configuration directed to blow a first anti-fuse to a second configuration directed to blow a second anti-fuse, yet still allow complete blowing of the first anti-fuse. Such circuitry may be applied to methods of repairing a memory device after testing. Data concerning available repair cells may be stored in at least one on-chip redundancy register.
摘要翻译：提供电路以允许将来自第一配置的输入信号的早期切换引导为将第一反熔丝吹向第二配置以引导第二反熔丝，但仍允许第一反熔丝完全吹动。这样的电路可以应用于在测试之后修复存储器件的方法。关于可用修复单元的数据可以存储在至少一个片上冗余寄存器中。

8. 发明申请

US20130003473A1 STACKED DEVICE REMAPPING AND REPAIR 有权
标题翻译：堆叠设备重新修复和维修
公开(公告)号：US20130003473A1
公开(公告)日：2013-01-03
申请号：US13616704
申请日：2012-09-14
申请人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
发明人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
IPC分类号： G11C7/10
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
摘要翻译：各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。描述其他实施例。

9. 发明申请

US20090224242A1 ISOLATION CIRCUIT 有权
标题翻译：隔离电路
公开(公告)号：US20090224242A1
公开(公告)日：2009-09-10
申请号：US12468482
申请日：2009-05-19
申请人： Timothy B. Cowles , Aron T. Lunde
发明人： Timothy B. Cowles , Aron T. Lunde
IPC分类号： H01L23/00 , H01L27/10 , H01L21/8232
CPC分类号： G01R31/2884
摘要： An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential, a first fuse device coupling the second source/drain terminal to a node, a second fuse device coupling the node to the first pad, a third pad operable to receive a signal to be applied to at least one die, and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node.
摘要翻译：一种隔离电路，包括具有栅极的第一晶体管，第一源极/漏极端子和第二源极/漏极端子，耦合到第一晶体管的栅极的第一焊盘，第一焊盘可操作以接收使能信号，第二焊盘，其耦合到第一晶体管的第一源极/漏极，第二焊盘可操作以接收接地电位;将第二源极/漏极端子耦合到节点的第一熔丝器件;将节点耦合到第一焊盘的第二熔丝器件第三焊盘，其可操作以接收要施加到至少一个管芯的信号;以及第二晶体管，其可操作以响应于由所述节点提供的控制信号选择性地将在第三焊盘处接收的信号传输到至少一个管芯。

10. 发明申请

US20090085613A1 LOW CURRENT WIDE VREF RANGE INPUT BUFFER 失效
标题翻译：低电流VREF范围输入缓冲器
公开(公告)号：US20090085613A1
公开(公告)日：2009-04-02
申请号：US12268782
申请日：2008-11-11
申请人： Timothy B. Cowles , Steve Casper
发明人： Timothy B. Cowles , Steve Casper
IPC分类号： H03K3/00
CPC分类号： H03K19/018528
摘要： A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.
摘要翻译：公开了一种低电流输入缓冲器。缓冲器使用自偏置N和P通道差分对，其输出端连接在一起。自偏置有助于减少电流消耗。 N沟道和P沟道差分对的组合导致了宽范围的参考电压和电源电压的对称性。

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