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1. 发明授权

US08499207B2 Memory devices and method for error test, recordation and repair 有权
标题翻译：内存设备和方法进行错误测试，记录和修复
公开(公告)号：US08499207B2
公开(公告)日：2013-07-30
申请号：US13559942
申请日：2012-07-27
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

2. 发明申请

US20110209011A1 METHOD FOR ERROR TEST, RECORDATION AND REPAIR 失效
标题翻译：错误测试，记录和修复方法
公开(公告)号：US20110209011A1
公开(公告)日：2011-08-25
申请号：US13098569
申请日：2011-05-02
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G06F11/20
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

3. 发明授权

US07941712B2 Method for error test, recordation and repair 有权
标题翻译：错误测试，记录和修复方法
公开(公告)号：US07941712B2
公开(公告)日：2011-05-10
申请号：US11714348
申请日：2007-03-06
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G11C29/00
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

4. 发明申请

US20120297257A1 MEMORY DEVICES AND METHOD FOR ERROR TEST, RECORDATION AND REPAIR 有权
标题翻译：用于错误测试，记录和修复的记忆装置和方法
公开(公告)号：US20120297257A1
公开(公告)日：2012-11-22
申请号：US13559942
申请日：2012-07-27
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G06F11/20
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

5. 发明授权

US08234527B2 Method for error test, recordation and repair 失效
标题翻译：错误测试，记录和修复方法
公开(公告)号：US08234527B2
公开(公告)日：2012-07-31
申请号：US13098569
申请日：2011-05-02
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

6. 发明授权

US07509543B2 Circuit and method for error test, recordation, and repair 失效
标题翻译：错误测试，记录和修复的电路和方法
公开(公告)号：US07509543B2
公开(公告)日：2009-03-24
申请号：US10464762
申请日：2003-06-17
申请人： Christian N. Mohr , Timothy B. Cowles
发明人： Christian N. Mohr , Timothy B. Cowles
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C17/18 , G11C11/401 , G11C29/24 , G11C29/44 , G11C29/70 , G11C29/838 , G11C2029/1208 , G11C2029/4402
摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
摘要翻译：在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。存储行地址还可以使用分段冗余来指导修复。作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

7. 发明授权

US07482855B2 Circuit and method for stable fuse detection 有权
标题翻译：用于稳定保险丝检测的电路和方法
公开(公告)号：US07482855B2
公开(公告)日：2009-01-27
申请号：US11897244
申请日：2007-08-29
申请人： Christian N. Mohr , Scott E. Smith
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.
摘要翻译：熔丝状态检测电路包括第一熔丝元件，第二熔丝元件和用于承载输出信号的输出端，所述输出信号表示当第一熔丝元件被吹制而第二熔丝元件未被吹出时的第一逻辑状态，当第一元件未吹出并且第二元件被吹动时，输出信号表示第二逻辑状态。熔丝状态检测电路产生其状态可从负触发事件中恢复的输出信号，并且能够将其自身解析为正确状态而无需复位脉冲。还提供了使用熔丝状态检测电路的方法，例如使用熔丝元件来控制电子电路内的设置的方法，包括使用一对熔丝元件来控制单个设置的改进。

8. 发明授权

US07276955B2 Circuit and method for stable fuse detection 有权
标题翻译：用于稳定保险丝检测的电路和方法
公开(公告)号：US07276955B2
公开(公告)日：2007-10-02
申请号：US11106100
申请日：2005-04-14
申请人： Christian N. Mohr , Scott E. Smith
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.
摘要翻译：熔丝状态检测电路包括第一熔丝元件，第二熔丝元件和用于承载输出信号的输出端，所述输出信号表示当第一熔丝元件被吹制而第二熔丝元件未被吹出时的第一逻辑状态，当第一元件未吹出并且第二元件被吹动时，输出信号表示第二逻辑状态。熔丝状态检测电路产生其状态可从负触发事件中恢复的输出信号，并且能够将其自身解析为正确状态而无需复位脉冲。还提供了使用熔丝状态检测电路的方法，例如使用熔丝元件来控制电子电路内的设置的方法，包括使用一对熔丝元件来控制单个设置的改进。

9. 发明授权

US07145817B2 Reduced power redundancy address decoder and comparison circuit 有权
标题翻译：减少冗余地址解码器和比较电路
公开(公告)号：US07145817B2
公开(公告)日：2006-12-05
申请号：US11015703
申请日：2004-12-17
申请人： Christian N. Mohr , Scott E. Smith
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： G11C7/00
CPC分类号： G11C29/83 , G11C29/844
摘要： A redundancy address decoder for a memory having at least one bank of memory segmented into a plurality of memory blocks. The redundancy address decoder includes a plurality of redundancy comparison circuitry coupled to a respective programmable element block storing addresses that are mapped to redundant memory of a memory plane. The redundancy address decoder further includes redundancy driver select logic coupled to each of the redundancy comparison circuitry to activate a selected one of the redundancy comparison circuitry for comparing a portion of a memory address corresponding to a memory location with the programmed addresses of the respective programmable element blocks, which leads to power reduction for column accesses to the memory device. The selection of the redundancy driver is based on the memory bank in which the memory location is located.
摘要翻译：一种用于存储器的冗余地址解码器，其具有被分割成多个存储块的至少一组存储器。冗余地址解码器包括耦合到存储映射到存储器平面的冗余存储器的地址的相应可编程元件块的多个冗余比较电路。冗余地址解码器还包括耦合到冗余比较电路中的每一个的冗余驱动器选择逻辑，以激活冗余比较电路中的所选择的一个，用于将对应于存储器位置的存储器地址的一部分与相应可编程元件的编程地址进行比较块，这导致对存储器设备的列访问的功率降低。冗余驱动器的选择基于存储器位置所在的存储体。

10. 发明授权

US06918072B2 Circuit and method for time-efficient memory repair 失效
标题翻译：电路和时间效率记忆修复方法
公开(公告)号：US06918072B2
公开(公告)日：2005-07-12
申请号：US09864682
申请日：2001-05-24
申请人： Timothy B. Cowles , Christian N. Mohr
发明人： Timothy B. Cowles , Christian N. Mohr
IPC分类号： G01R31/28 , G11C11/401 , G11C11/413 , G11C16/02 , G11C29/00 , G11C29/12 , G11C29/44
CPC分类号： G11C29/72 , G11C29/44
摘要： Circuitry is provided to allow early switching of input signals from a first configuration directed to blow a first anti-fuse to a second configuration directed to blow a second anti-fuse, yet still allow complete blowing of the first anti-fuse. Such circuitry may be applied to methods of repairing a memory device after testing. Data concerning available repair cells may be stored in at least one on-chip redundancy register.
摘要翻译：提供电路以允许将来自第一配置的输入信号的早期切换引导为将第一反熔丝吹向第二配置以引导第二反熔丝，但仍允许第一反熔丝完全吹动。这样的电路可以应用于在测试之后修复存储器件的方法。关于可用修复单元的数据可以存储在至少一个片上冗余寄存器中。

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