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1. 发明授权

US09026887B2 Physical page, logical page, and codeword correspondence 有权
标题翻译：物理页面，逻辑页面和代码字对应
公开(公告)号：US09026887B2
公开(公告)日：2015-05-05
申请号：US13421088
申请日：2012-03-15
申请人： Troy A. Manning , Troy D. Larsen , Martin L. Culley
发明人： Troy A. Manning , Troy D. Larsen , Martin L. Culley
IPC分类号： G11C29/00 , G06F11/10 , G06F9/45
CPC分类号： G06F11/1068 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F3/0688 , G06F3/0689 , G06F8/44 , G06F11/108 , G06F2211/104 , G11C29/52
摘要： The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
摘要翻译：本公开包括用于物理页面，逻辑页面和码字对应的装置和方法。许多方法包括将多个数据的逻辑页面的错误编码为码字的数量并将码字的数量写入存储器的多个物理页面。数据的逻辑页数可以不同于存储器的物理页数。

2. 发明授权

US08732557B2 Data protection across multiple memory blocks 有权
标题翻译：跨多个内存块的数据保护
公开(公告)号：US08732557B2
公开(公告)日：2014-05-20
申请号：US13118638
申请日：2011-05-31
申请人： Sampath K. Ratnam , Troy D. Larsen , Doyle W. Rivers , Troy A. Manning , Martin L. Culley
发明人： Sampath K. Ratnam , Troy D. Larsen , Doyle W. Rivers , Troy A. Manning , Martin L. Culley
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G06F11/10 , G06F11/108 , G11C11/5628 , G11C16/0483
摘要： Data protection across multiple memory blocks can include writing a first portion of a codeword in a first memory block and writing a second portion of the codeword in a second memory block. The first memory block and the second memory block can be different memory blocks. The first portion of the codeword can be written in a different location in the first memory block than the second portion of the codeword is written in the second memory block.
摘要翻译：跨多个存储器块的数据保护可以包括在第一存储器块中写入码字的第一部分并将码字的第二部分写入第二存储器块。第一存储器块和第二存储器块可以是不同的存储器块。码字的第一部分可以被写入第一存储块中的不同位置，而不是将码字的第二部分写入第二存储块。

3. 发明授权

US08417914B2 Memory address translation 有权
标题翻译：内存地址转换
公开(公告)号：US08417914B2
公开(公告)日：2013-04-09
申请号：US12985787
申请日：2011-01-06
申请人： Troy A. Manning , Martin L. Culley , Troy D. Larsen
发明人： Troy A. Manning , Martin L. Culley , Troy D. Larsen
IPC分类号： G06F12/00
CPC分类号： G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02D10/13
摘要： The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
摘要翻译：本公开包括用于存储器地址转换的装置，系统和方法。一个或多个实施例包括存储器阵列和耦合到阵列的控制器。阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。

4. 发明申请

US20130003473A1 STACKED DEVICE REMAPPING AND REPAIR 有权
标题翻译：堆叠设备重新修复和维修
公开(公告)号：US20130003473A1
公开(公告)日：2013-01-03
申请号：US13616704
申请日：2012-09-14
申请人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
发明人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
IPC分类号： G11C7/10
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
摘要翻译：各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。描述其他实施例。

5. 发明申请

US20100106997A1 METHOD AND APPARATUS FOR GENERATING EXPECT DATA FROM A CAPTURED BIT PATTERN, AND MEMORY DEVICE USING SAME 有权
标题翻译：用于从捕获的位模式生成预期数据的方法和装置，以及使用相同的存储器件
公开(公告)号：US20100106997A1
公开(公告)日：2010-04-29
申请号：US12649137
申请日：2009-12-29
申请人： Troy A. Manning
发明人： Troy A. Manning
IPC分类号： G06F1/04
CPC分类号： G11C29/022 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C11/4096 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAMs.
摘要翻译：为具有已知序列的一系列应用数据信号产生预期数据信号，以确定数据信号组是否被适当地捕获。捕获应用数据信号的第一组，并从捕获的第一组生成一组期望数据信号。然后当第二组对应于期望数据信号组时，捕获并确定第二组应用数据信号以被适当地捕获。以这种方式，当捕获的一系列数据信号从期望的捕获点在时间上移动时，将后续捕获的数据信号与其正确的预期数据信号进行比较，以便确定该组虽然在时间上移动仍然被正确捕获。模式发生器以这种方式生成期望数据信号，并且可以用于各种集成电路，例如SLDRAM。

6. 发明申请

US20090248970A1 DUAL EDGE COMMAND 有权
标题翻译：双边命令
公开(公告)号：US20090248970A1
公开(公告)日：2009-10-01
申请号：US12478270
申请日：2009-06-04
申请人： Joo S. Choi , Troy A. Manning , Brent Keeth
发明人： Joo S. Choi , Troy A. Manning , Brent Keeth
IPC分类号： G06F12/06 , G06F12/04
CPC分类号： G11C11/4076 , G06F12/0207 , G06F13/1668 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C11/408 , G11C11/409
摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
摘要翻译：一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

7. 发明授权

US07299329B2 Dual edge command in DRAM 有权
标题翻译： DRAM中的双边沿命令
公开(公告)号：US07299329B2
公开(公告)日：2007-11-20
申请号：US10767555
申请日：2004-01-29
申请人： Joo S. Choi , Troy A. Manning , Brent Keeth
发明人： Joo S. Choi , Troy A. Manning , Brent Keeth
IPC分类号： G06F12/00
CPC分类号： G11C11/4076 , G06F12/0207 , G06F13/1668 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C11/408 , G11C11/409
摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
摘要翻译：一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

8. 发明授权

US06882579B2 Memory device and method having data path with multiple prefetch I/O configurations 失效
标题翻译：具有多个预取I / O配置的数据路径的存储器件和方法
公开(公告)号：US06882579B2
公开(公告)日：2005-04-19
申请号：US10705388
申请日：2003-11-10
申请人： Brent Keeth , Brian Johnson , Troy A. Manning
发明人： Brent Keeth , Brian Johnson , Troy A. Manning
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
摘要翻译：存储器件可以在高模式或低速模式下操作。在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线终端。在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个巴士总站。

9. 发明授权

US06853590B2 Methods and apparatus for reading memory device register data 失效
标题翻译：读取存储器件寄存器数据的方法和装置
公开(公告)号：US06853590B2
公开(公告)日：2005-02-08
申请号：US10691068
申请日：2003-10-21
申请人： Troy A. Manning
发明人： Troy A. Manning
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1051
摘要： A methods and apparatus for reading register data from a memory device and outputting the register data to external data terminals of the memory device that outputs a first set of data bits from a memory array to the external terminals responsive to a first addressing signal. A register stores data, and outputs a second set of data bits responsive to a second addressing signal. A coupling circuit receives the second set of data bits, processes the data bits, and outputs a third set of data bits corresponding to the second set of data bits responsive to an enabling signal. A data path circuit that is coupled to the memory array to receive the first set of data bits is coupled to the coupling circuit to receive the third plurality of data bits, and to the external terminals. The data path circuit transmits the data bits received to the external terminals of the memory device.
摘要翻译：一种用于从存储器件读取寄存器数据并将寄存器数据输出到存储器件的外部数据端的方法和装置，其响应于第一寻址信号从存储器阵列向外部端子输出第一组数据位。寄存器存储数据，并且响应于第二寻址信号输出第二组数据位。耦合电路接收第二组数据位，处理数据位，并响应于使能信号输出与第二组数据位对应的第三组数据位。耦合到存储器阵列以接收第一组数据位的数据路径电路耦合到耦合电路以接收第三多个数据位以及外部端。数据路径电路将接收的数据位发送到存储器件的外部端子。

10. 发明授权

US06851016B2 System latency levelization for read data 失效
标题翻译：读取数据的系统延迟级别化
公开(公告)号：US06851016B2
公开(公告)日：2005-02-01
申请号：US10720183
申请日：2003-11-25
申请人： Jeffery W. Janzen , Brent Keeth , Kevin J. Ryan , Troy A. Manning , Brian Johnson
发明人： Jeffery W. Janzen , Brent Keeth , Kevin J. Ryan , Troy A. Manning , Brian Johnson
IPC分类号： G06F12/00 , G11C7/10 , G11C7/22 , G11C11/407
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
摘要翻译：在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统读延迟。

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