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1. 发明授权

US5553244A Reflexively sizing memory bus interface 失效
标题翻译：反映尺寸的内存总线接口
公开(公告)号：US5553244A
公开(公告)日：1996-09-03
申请号：US387964
申请日：1995-02-10
申请人： Thomas M. Norcross , William V. Miller
发明人： Thomas M. Norcross , William V. Miller
IPC分类号： G06F12/06 , G06F12/04 , G06F13/16 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4018
摘要： A reflexively scaling memory bus interface system and method allows the implementation of an ISA bus peripheral card that will effectively operate within the decoded memory space of another sixteen bit card while using only the external memory components required for an eight bit interface. The same peripheral card will also be compatible in a system with other eight bit cards located in a corresponding memory space. The reflexively sizing memory bus interface responds automatically to memory accesses that vary in data bus width (i.e., eight or sixteen bits) by directly or indirectly monitoring feedback signals from other devices on the bus. This technique solves the problem of integrating eight and sixteen bit cards on the ISA bus.
摘要翻译：反向缩放的存储器总线接口系统和方法允许实现ISA总线外围卡，其将仅在使用八位接口所需的外部存储器组件的同时在另一十六位卡的解码存储器空间内有效地操作。相同的外围卡也将与位于相应存储器空间中的其他八位卡的系统兼容。自动调整大小的存储器总线接口通过直接或间接监视总线上其他设备的反馈信号，自动响应数据总线宽度（即八位或十六位）变化的存储器访问。这种技术解决了在ISA总线上集成8位和16位位卡的问题。

2. 发明申请

US20130094313A1 COLLISION PREVENTION IN A DUAL PORT MEMORY 有权
标题翻译：双端口记忆中的碰撞预防
公开(公告)号：US20130094313A1
公开(公告)日：2013-04-18
申请号：US13275920
申请日：2011-10-18
申请人： Steven C. Sullivan , William V. Miller
发明人： Steven C. Sullivan , William V. Miller
IPC分类号： G11C7/00
CPC分类号： G11C7/1075
摘要： A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row.
摘要翻译：双端口存储器包括用于防止冲突的机构。存储器包括以行和列布置的双端口位单元，并且每个位单元存储数据位。存储器还包括字线单元，其可以向每行位单元提供相应的写入字线信号和相应的读取字线信号。字线单元还可以基于指示是否对给定行执行写入操作的地址信息来选择性地禁止给定行的读取字线信号。

3. 发明授权

US5774684A Integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitration 失效
标题翻译：具有多种功能的集成电路根据分布式总线访问和控制仲裁共享多条内部信号总线
公开(公告)号：US5774684A
公开(公告)日：1998-06-30
申请号：US730996
申请日：1996-10-08
申请人： Ralph Warren Haines , Dan Craig O'Neill , Stephen C. Pries , William V. Miller , Kent B. Waterson , David S. Weinman , Michael J. Shay , Jianhua Helen Pang , Daniel R. Herrington , Brian J. Marley , John R. Gunther , Alexander Perez , James Andrew Colgan , Robert James Divivier
发明人： Ralph Warren Haines , Dan Craig O'Neill , Stephen C. Pries , William V. Miller , Kent B. Waterson , David S. Weinman , Michael J. Shay , Jianhua Helen Pang , Daniel R. Herrington , Brian J. Marley , John R. Gunther , Alexander Perez , James Andrew Colgan , Robert James Divivier
IPC分类号： G06F11/36 , G06F13/368 , H01J13/00
CPC分类号： G06F11/3652 , G06F13/368
摘要： An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions. Maximum performance is thereby achieved from the circuit functions accessed most frequently, while still achieving high performance from those circuit functions accessed less frequently. The IC may provided with a processor core with features that support In-Circuit Emulation (ICE).
摘要翻译：集成电路（IC）包括多个电路和功能，它们根据分布式总线访问和控制仲裁共享多个内部信号总线，三个物理和五个逻辑。多个内部信号总线由三层内部电路功能共享：中央处理单元和DMA控制器; DRAM控制器和总线接口单元; 和外围接口电路，如PCMCIA和显示控制器。两条物理总线对应于两条逻辑总线，用于IC内的通信。第三物理总线对应于三条逻辑总线，用于IC和IC外部的电路之间的通信。用于访问和控制各种信号总线的仲裁分布在三层内部电路功能内部。因此，从最频繁访问的电路功能可以实现最大性能，同时仍能从较少频繁访问的电路功能中获得高性能。 IC可以提供具有支持在线仿真（ICE）的特征的处理器核心。

4. 发明授权

US08472267B2 Late-select, address-dependent sense amplifier 有权
标题翻译：后期选择，地址相关的读出放大器
公开(公告)号：US08472267B2
公开(公告)日：2013-06-25
申请号：US13164382
申请日：2011-06-20
申请人： Abhijeet R. Tanpure , Steven C. Sullivan , William V. Miller , Jason A. Frerich
发明人： Abhijeet R. Tanpure , Steven C. Sullivan , William V. Miller , Jason A. Frerich
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/025
摘要： Sense amplifiers in a memory may be activated and deactivated. In one embodiment, a processor may include a memory. The memory may include a number of sense amplifiers. Based on a late arriving address bit of an address used to access data from the memory, a sense amplifier may be activated while another sense amplifier may be deactivated.
摘要翻译：存储器中的感测放大器可以被激活并被去激活。在一个实施例中，处理器可以包括存储器。存储器可以包括多个读出放大器。基于用于从存储器访问数据的地址的晚到地址位，可以激活读出放大器，而另一个读出放大器可以被去激活。

5. 发明授权

US07594103B1 Microprocessor and method of processing instructions for responding to interrupt condition 有权
标题翻译：微处理器和处理中断条件响应指令的方法
公开(公告)号：US07594103B1
公开(公告)日：2009-09-22
申请号：US10294578
申请日：2002-11-15
申请人： Paul J. Patchen , William V. Miller
发明人： Paul J. Patchen , William V. Miller
IPC分类号： G06F9/30
CPC分类号： G06F9/3804
摘要： A pipeline processing microprocessor includes a storage unit for storing instructions and a fetch unit for requesting and fetching an instruction from the instructions in the storage unit. Upon an interrupt condition, the fetch unit eliminates from a request queue a previously requested instruction that precedes the interrupt condition.
摘要翻译：流水线处理微处理器包括用于存储指令的存储单元和用于从存储单元中的指令请求和获取指令的提取单元。在中断条件下，提取单元从请求队列中消除先前请求的中断条件之前的指令。

6. 发明授权

US07210051B2 System and method for handling state change conditions by a program status register 有权
标题翻译：通过程序状态寄存器来处理状态变化的系统和方法
公开(公告)号：US07210051B2
公开(公告)日：2007-04-24
申请号：US10703279
申请日：2003-11-07
申请人： Paul J. Patchen , William V. Miller
发明人： Paul J. Patchen , William V. Miller
IPC分类号： G06F1/04
CPC分类号： G06F9/30101 , G06F9/3863
摘要： An improved program status register is disclosed with a feature to handle state change for a processor and its memory subsystem. The program status register comprises a clock, at least one update value for updating the program status register to a second value from a first value when an update enable signal is received, a sampled program status register storing the first value of the program status register, and a state change sampling register generating a synchronized state change signal from a state change indication signal and the clock. When the update enable signal is initially received and a state change indication signal is further received thereafter during a first clock cycle, an updated output of the program status register is restored through a first selection module triggered by the synchronized state change signal to the first value in a second clock cycle following the first clock cycle.
摘要翻译：公开了一种改进的程序状态寄存器，其具有处理处理器及其存储器子系统的状态改变的特征。程序状态寄存器包括时钟，用于当接收到更新使能信号时从第一值将程序状态寄存器更新为第二值的至少一个更新值，存储程序状态寄存器的第一值的采样程序状态寄存器，以及状态改变采样寄存器，其从状态改变指示信号和时钟产生同步状态改变信号。当在第一时钟周期中最初接收到更新使能信号并且此后进一步接收状态改变指示信号时，通过由同步状态改变信号触发到第一值的第一选择模块恢复程序状态寄存器的更新输出在第一个时钟周期之后的第二个时钟周期。

7. 发明授权

US07000131B2 Apparatus and method for assuming mastership of a bus 有权
标题翻译：假设公共汽车主管的装置和方法
公开(公告)号：US07000131B2
公开(公告)日：2006-02-14
申请号：US10713838
申请日：2003-11-14
申请人： William V. Miller , Richard L. Duncan
发明人： William V. Miller , Richard L. Duncan
IPC分类号： G06F1/32 , G06F13/00
CPC分类号： G06F13/364 , Y02D10/14
摘要： The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one embodiment, the bus master is provided in the form of an integrated circuit comprising clock control logic that is configured to disable a clock signal that is otherwise delivered to functional circuitry contained within the integrated circuit during a period of time between the request for mastership of a bus and the grant of that request.
摘要翻译：本发明一般涉及用于减少在多总线主系统中使用的总线主电路部件的多余功耗的装置和方法。在一个实施例中，总线主机以集成电路的形式提供，该集成电路包括时钟控制逻辑，时钟控制逻辑被配置为在请求主控之前的一段时间内禁用否则传送到集成电路内的功能电路的时钟信号的公共汽车和批准该请求。

8. 发明授权

US4195075A Method and device for controlling insects on livestock 失效
标题翻译：用于控制牲畜昆虫的方法和装置
公开(公告)号：US4195075A
公开(公告)日：1980-03-25
申请号：US944513
申请日：1978-09-20
申请人： William V. Miller
发明人： William V. Miller
IPC分类号： A01K11/00 , A01N25/34 , A01N37/38 , A01K13/00
CPC分类号： A01K11/001 , A01N25/34 , A01N37/38
摘要： Cattle and other livestock are protected from insects such as face flies, horn flies, ticks and the like by use of a uniquely effective insect control device attached to the animal. The insect control device comprises a polymeric resin matrix, preferably in the form of an ear tag or ear band, containing a liquid, insecticidally-active isomer of alpha-cyano-3-phenoxy-benzyl-alpha-isopropyl-4-chlorophenyl acetate.
摘要翻译：通过使用附着在动物上的唯一有效的昆虫控制装置，可以保护牛和其他牲畜免受诸如苍蝇，角蝇，蜱等的昆虫。昆虫控制装置包括优选为耳标或耳带形式的聚合物树脂基质，其含有α-氰基-3-苯氧基 - 苄基-α-异丙基-4-氯苯基乙酸酯的液体杀虫活性异构体。

9. 发明申请

US20130111090A1 QUEUE ARBITRATION USING NON-STALLING REQUEST INDICATION 有权
标题翻译：使用非存储请求指示的队列仲裁
公开(公告)号：US20130111090A1
公开(公告)日：2013-05-02
申请号：US13286074
申请日：2011-10-31
申请人： William V. Miller , Chameera R. Fernando
发明人： William V. Miller , Chameera R. Fernando
IPC分类号： G06F13/38
CPC分类号： G06F13/1663
摘要： Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.
摘要翻译：公开了关于多个主电路和多个目标电路之间的请求仲裁的技术。在一个实施例中，一种装置包括耦合到目标电路的多个请求队列的仲裁单元。每个请求队列被配置为存储由多个主电路中的相应一个产生的请求。仲裁单元被配置为基于指示通过主电路将请求提交给多个请求队列的顺序的信息在多个请求队列中的请求之间进行仲裁。在一些实施例中，多个主电路中的每一个被配置为向目标电路提供每个请求以指示已经提交了请求的指示，并且仲裁单元被配置为根据请求确定所请求的顺序就提交的适应症。

10. 发明申请

US20120124328A1 Translation Lookaside Buffer Structure Including an Output Comparator 有权
标题翻译：包括输出比较器的翻译后备缓冲区结构
公开(公告)号：US20120124328A1
公开(公告)日：2012-05-17
申请号：US13097286
申请日：2011-04-29
申请人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
发明人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
IPC分类号： G06F12/10
CPC分类号： H03K19/096 , G06F12/1027 , G11C7/062 , Y02D10/13
摘要： A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.
摘要翻译：处理器包括包括数据阵列和比较单元的翻译后备缓冲器（TLB）。数据阵列包括多个条目，每个条目被配置为存储相应的翻译的物理地址。响应于对TLB的给定条目的读取访问，数据阵列被配置为在特定时钟周期内输出存储在给定条目中的相应翻译的物理地址。此外，比较单元可以被配置为将由数据阵列输出的相应翻译的物理地址与多个附加地址进行比较。比较单元还可以被配置为为特定时钟周期内的每个附加地址提供命中指示。

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