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1. 发明授权

US4497497A Oil ring assembly with annular expander spring 失效
标题翻译：带环形膨胀弹簧的油环组件
公开(公告)号：US4497497A
公开(公告)日：1985-02-05
申请号：US623010
申请日：1984-06-21
申请人： Jerome L. Berti , Paul J. Patchen
发明人： Jerome L. Berti , Paul J. Patchen
IPC分类号： F16J9/06 , F16J9/20 , F16J9/22
CPC分类号： F16J9/062
摘要： An oil ring and coiled expander spring assembly in which the groove for the expander spring is of unique configuration and possesses a unique relationship with the expander spring.
摘要翻译：一种油环和螺旋膨胀弹簧组件，其中用于膨胀弹簧的槽具有独特的构造，并且与膨胀弹簧具有独特的关系。

2. 发明授权

US4965524A Glitch free clock select 失效
标题翻译：无毛刺时钟选择
公开(公告)号：US4965524A
公开(公告)日：1990-10-23
申请号：US393011
申请日：1989-08-11
申请人： Paul J. Patchen
发明人： Paul J. Patchen
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： Clock select circuitry is provided which allows CPU operation at the crystal frequency or one-half the crystal frequency. Frequency selection is accomplished under CPU control and circuitry is added to insure that the a glitch free clock change can be performed on the fly. The glitch free clock select insures that no half T state is less than what a full speed half T state would be. By gating the appropriate phases of the half speed clock and the full speed clock to control the clocking of a flip flop, the point at which the clock selection multiplexer is switched can be controlled. In speeding up the clock, the speed change occurs on the falling edge of the full speed clock provided that the half speed clock is low. When slowing down the clock, the speed change occurs on the rising edge of the half speed clock.
摘要翻译：提供时钟选择电路，允许CPU以晶体频率工作或晶体频率的一半。在CPU控制下实现频率选择，并添加电路，以确保无故障时钟更改可以在飞行中执行。无毛刺时钟选择保证没有半T状态小于全速半T状态。通过选通半速时钟和全速时钟的适当相位来控制触发器的时钟，可以控制时钟选择多路复用器切换的时间点。在加速时钟时，速度变化发生在全速时钟的下降沿，只要半速时钟为低电平。当时钟减慢时，速度变化发生在半速时钟的上升沿。

3. 发明授权

US4851716A Single plane dynamic decoder 失效
标题翻译：单平面动态解码器
公开(公告)号：US4851716A
公开(公告)日：1989-07-25
申请号：US204637
申请日：1988-06-09
申请人： William M. Needles , Paul J. Patchen
发明人： William M. Needles , Paul J. Patchen
IPC分类号： H03K19/096 , H03M7/00
CPC分类号： H03K19/0963 , H03M7/005
摘要： A single plane dynamic decoder wherein a typical decoder row comprises a P-channel transistor connected between a positive supply and a first node, a second N-channel transistor connected between ground potential and a second node, and a plurality of series-connected devices connected between the first node and the second node. The gates of the intermediate N-channel devices are connected to a corresponding input signal such that the intermediate devices are enabled or disabled depending on the state of the associated input. The gate of the P-channel device is connected to a clock signal such that it is enabled by a first clock phase and disabled by a second clock phase. The N-channel device is connected to the clock signal such that it is enabled by the second clock phase and disabled by the first clock phase. Thus, the first node is precharged when the P-channel device is enabled. This precharge activity occurs serially and hierarchically down the row depending on the state of the respective input signals. When the clock state changes, the N-channel device is enabled and the second node is discharged. The discharging of nodes will propagate serially up the row depending upon the state of the input signals. Therefore, the intermediate devices provide a NAND function. If each of the first nodes of adjacent rows are connected to a single output node, a wired-OR function results. Thus, a multi-term single plane dynamic decoder is provided that has the same functionality as a conventional two-plane AND-OR functional array or a static logic array.
摘要翻译：一种单平面动态解码器，其中典型的解码器行包括连接在正电源和第一节点之间的P沟道晶体管，连接在地电位和第二节点之间的第二N沟道晶体管和连接的多个串联连接的器件在第一节点和第二节点之间。中间N沟道器件的栅极连接到相应的输入信号，使得中间器件根据相关输入的状态被使能或禁止。 P沟道器件的栅极连接到时钟信号，使得其被第一时钟相位使能并被第二时钟相位禁止。 N沟道器件连接到时钟信号，使得其由第二时钟相位使能并被第一时钟相位禁止。因此，当P信道设备被使能时，第一节点被预充电。这种预充电活动根据各个输入信号的状态在行上连续和分层地发生。当时钟状态改变时，N通道器件被使能，第二个节点被释放。根据输入信号的状态，节点的放电将逐行传播。因此，中间装置提供NAND功能。如果相邻行的每个第一个节点都连接到单个输出节点，则会产生有线OR功能。因此，提供了具有与常规双平面AND-OR功能阵列或静态逻辑阵列相同的功能的多项单平面动态解码器。

4. 发明授权

US07594103B1 Microprocessor and method of processing instructions for responding to interrupt condition 有权
标题翻译：微处理器和处理中断条件响应指令的方法
公开(公告)号：US07594103B1
公开(公告)日：2009-09-22
申请号：US10294578
申请日：2002-11-15
申请人： Paul J. Patchen , William V. Miller
发明人： Paul J. Patchen , William V. Miller
IPC分类号： G06F9/30
CPC分类号： G06F9/3804
摘要： A pipeline processing microprocessor includes a storage unit for storing instructions and a fetch unit for requesting and fetching an instruction from the instructions in the storage unit. Upon an interrupt condition, the fetch unit eliminates from a request queue a previously requested instruction that precedes the interrupt condition.
摘要翻译：流水线处理微处理器包括用于存储指令的存储单元和用于从存储单元中的指令请求和获取指令的提取单元。在中断条件下，提取单元从请求队列中消除先前请求的中断条件之前的指令。

5. 发明授权

US07210051B2 System and method for handling state change conditions by a program status register 有权
标题翻译：通过程序状态寄存器来处理状态变化的系统和方法
公开(公告)号：US07210051B2
公开(公告)日：2007-04-24
申请号：US10703279
申请日：2003-11-07
申请人： Paul J. Patchen , William V. Miller
发明人： Paul J. Patchen , William V. Miller
IPC分类号： G06F1/04
CPC分类号： G06F9/30101 , G06F9/3863
摘要： An improved program status register is disclosed with a feature to handle state change for a processor and its memory subsystem. The program status register comprises a clock, at least one update value for updating the program status register to a second value from a first value when an update enable signal is received, a sampled program status register storing the first value of the program status register, and a state change sampling register generating a synchronized state change signal from a state change indication signal and the clock. When the update enable signal is initially received and a state change indication signal is further received thereafter during a first clock cycle, an updated output of the program status register is restored through a first selection module triggered by the synchronized state change signal to the first value in a second clock cycle following the first clock cycle.
摘要翻译：公开了一种改进的程序状态寄存器，其具有处理处理器及其存储器子系统的状态改变的特征。程序状态寄存器包括时钟，用于当接收到更新使能信号时从第一值将程序状态寄存器更新为第二值的至少一个更新值，存储程序状态寄存器的第一值的采样程序状态寄存器，以及状态改变采样寄存器，其从状态改变指示信号和时钟产生同步状态改变信号。当在第一时钟周期中最初接收到更新使能信号并且此后进一步接收状态改变指示信号时，通过由同步状态改变信号触发到第一值的第一选择模块恢复程序状态寄存器的更新输出在第一个时钟周期之后的第二个时钟周期。

6. 发明授权

US4862482A Receiver for Manchester encoded data 失效
标题翻译：曼彻斯特编码数据接收器
公开(公告)号：US4862482A
公开(公告)日：1989-08-29
申请号：US207772
申请日：1988-06-16
申请人： Paul J. Patchen
发明人： Paul J. Patchen
IPC分类号： H03M5/12 , H04L7/033 , H04L7/10
CPC分类号： H03M5/12 , H04L7/0331 , H04L7/10
摘要： A receiver for extracting binary data from a Manchester-encoded input signal. Sampling logic samples the input signal at a frequency greater than the bit cell rate to detect input edges. The sampling logic output is divided to provide a sampling clock having a frequency greater than the bit cell rate and which is synchronized with the input signal. The sampling clock is then utilized to sample the first bit cell half of the sampled input signal. The value obtained by sampling the first bit cell half is then inverted to provide extracted binary data.
摘要翻译：用于从曼彻斯特编码的输入信号中提取二进制数据的接收器。采样逻辑以大于位单元速率的频率对输入信号进行采样，以检测输入边沿。采样逻辑输出被分割以提供具有大于位单元速率的频率并且与输入信号同步的采样时钟。然后采样采样时钟采样采样输入信号的第一位单元格一半。然后将通过对第一位单元格半进行采样获得的值反转，以提供提取的二进制数据。

7. 发明授权

US5748981A Microcontroller with in-circuit user programmable microcode 失效
标题翻译：具有在线用户可编程微代码的微控制器
公开(公告)号：US5748981A
公开(公告)日：1998-05-05
申请号：US748970
申请日：1996-11-13
申请人： Paul J. Patchen , Hon C. Fung , Fred Leung , Steven McGinness
发明人： Paul J. Patchen , Hon C. Fung , Fred Leung , Steven McGinness
IPC分类号： G06F9/24 , G06F9/00
CPC分类号： G06F9/24
摘要： An architecture is described for a single chip microcontroller wherein the microcode stored in the microcontroller's program memory may be easily modified without refabrication or removal of the microcontroller from its target environment. This is made possible by the utilization of a RAM based architecture for program memory instead of the traditional ROM based architecture.
摘要翻译：针对单芯片微控制器描述了架构，其中存储在微控制器的程序存储器中的微代码可以容易地被修改，而不需要从其目标环境重新制造或去除微控制器。这可以通过使用基于RAM的架构来实现程序存储而不是传统的基于ROM的架构。

8. 发明授权

US4970407A Asynchronously loadable D-type flip-flop 失效
标题翻译：异步加载D型触发器
公开(公告)号：US4970407A
公开(公告)日：1990-11-13
申请号：US379684
申请日：1989-07-12
申请人： Paul J. Patchen
发明人： Paul J. Patchen
IPC分类号： H03K3/3562
CPC分类号： H03K3/35625
摘要： A conventional D-type flip-flop transfers the data input D to a first output Q and a second output Q', where the second output Q' is the complement of the first output Q, on the transitions of a clock signal CK. This involves the transfer of data from a master latch and a series-connected slave latch which are loaded on alternating phases of the clock signal CK. The present invention provides for asynchronous loading of replacement data into the flip-flop by using a tri-stable buffer in both the master and slave latches. In response to a load signal LD, replacement data is injected into the master and slave latches overriding the current value stored at the Q and Q' outputs. This occurs because the load signal disables the normally active buffers while activating the loading buffers causing the normally active data path to go the tri-state condition. The state of the clock signal CK is of no importance to the outcome of the asynchronous load operation since both the master and the slave latch are overwritten during the load phase.
摘要翻译：传统的D型触发器在时钟信号CK的转变上将数据输入端D传送到第一输出端口Q和第二输出端口Q'，其中第二输出端口Q'是第一输出端口Q的补码。这涉及从时钟信号CK的交变相位上加载的主锁存器和串联从锁存器传送数据。本发明提供了通过在主锁存器和从锁存器两者中使用三稳态缓冲器来将替换数据异步加载到触发器中。响应于负载信号LD，替换数据被注入到主锁存器和从锁存器中以覆盖存储在Q和Q'输出端的当前值。这是因为负载信号禁用正常活动的缓冲区，同时激活加载缓冲区，导致正常活动数据路径进入三态条件。时钟信号CK的状态对于异步负载操作的结果不重要，因为在负载阶段都主写和从锁存器被重写。

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