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1. 发明授权

US08949573B2 Translation lookaside buffer structure including an output comparator 有权
标题翻译：翻译后备缓冲结构包括一个输出比较器
公开(公告)号：US08949573B2
公开(公告)日：2015-02-03
申请号：US13097286
申请日：2011-04-29
申请人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
发明人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
IPC分类号： G06F12/00 , H03K19/096 , G06F12/10 , G11C7/06
CPC分类号： H03K19/096 , G06F12/1027 , G11C7/062 , Y02D10/13
摘要： A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.
摘要翻译：处理器包括包括数据阵列和比较单元的翻译后备缓冲器（TLB）。数据阵列包括多个条目，每个条目被配置为存储相应的翻译的物理地址。响应于对TLB的给定条目的读取访问，数据阵列被配置为在特定时钟周期内输出存储在给定条目中的相应翻译的物理地址。此外，比较单元可以被配置为将由数据阵列输出的相应翻译的物理地址与多个附加地址进行比较。比较单元还可以被配置为为特定时钟周期内的每个附加地址提供命中指示。

2. 发明授权

US08570824B2 Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation 有权
标题翻译：存储器具有隔离单元，用于在保持模式操作期间将存储阵列与共享I / O隔离
公开(公告)号：US08570824B2
公开(公告)日：2013-10-29
申请号：US13356786
申请日：2012-01-24
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/02
CPC分类号： G11C5/063 , G11C7/06 , G11C11/4091 , G11C2207/002
摘要： A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
摘要翻译：存储器包括在多个存储阵列之间共享的I / O单元。共享I / O单元提供阵列的输出数据。存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

3. 发明申请

US20130135955A1 MEMORY DEVICE INCLUDING A RETENTION VOLTAGE RESISTOR 审中-公开
标题翻译：包含保持电压电阻的存储器件
公开(公告)号：US20130135955A1
公开(公告)日：2013-05-30
申请号：US13305796
申请日：2011-11-29
申请人： Edward M. McCombs , Kenneth W. Jones
发明人： Edward M. McCombs , Kenneth W. Jones
IPC分类号： G11C5/14
CPC分类号： G11C5/148
摘要： A mechanism for providing retention mode voltage to a memory storage array includes a resistor coupled between a power supply and a power rail of the storage array. The power rail may distribute an operating current to the bit cells of the storage array. The resistor may provide a path for current to the power rail from the power supply during operation in a retention mode. In addition, a switching device coupled between the power supply and the power rail, in parallel with the resistor, may convey operational current to the power rail from the power supply during operation in a normal mode.
摘要翻译：用于向存储器阵列提供保持模式电压的机构包括耦合在电源和存储阵列的电源轨之间的电阻器。电源轨可以将工作电流分配给存储阵列的位单元。在保持模式下，电阻器可以在操作期间从电源提供电流到电力轨的路径。此外，耦合在电源和电源轨之间的与电阻并联的开关装置可以在正常模式下操作期间将来自电源的工作电流传送到电源轨。

4. 发明授权

US08837226B2 Memory including a reduced leakage wordline driver 有权
标题翻译：存储器包括减少泄漏字线驱动器
公开(公告)号：US08837226B2
公开(公告)日：2014-09-16
申请号：US13286351
申请日：2011-11-01
申请人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
发明人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
IPC分类号： G11C11/34 , G11C8/08
CPC分类号： G11C8/08
摘要： A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.
摘要翻译：存储器包括具有减少泄漏的字线驱动器。存储器包括耦合到第一电压源的存储阵列以及包括驱动器反相器的多个字线驱动器单元。在低功率模式期间，耦合到字线电路的电压源的电压被减小或去除，而耦合到存储阵列的电压源的电压至少保持在保持电压。此外，p型晶体管耦合在阵列电压源和字线驱动器反相器的输入之间，从而将字线驱动器反相器的输出保持在低逻辑电平以防止意外的字线触发。

5. 发明授权

US08553472B2 Memory with a shared I/O including an output data latch having an integrated clamp 有权
标题翻译：具有共享I / O的存储器，包括具有集成钳位的输出数据锁存器
公开(公告)号：US08553472B2
公开(公告)日：2013-10-08
申请号：US13311340
申请日：2011-12-05
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106
摘要： A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.
摘要翻译：存储器包括在多个存储阵列之间共享的共享I / O单元，提供来自阵列的输出数据。共享I / O包括具有集成输出钳位的输出锁存器。 I / O单元可以被配置为经由数据输出信号路径从存储阵列提供输出数据。 I / O单元包括输出锁存器，其被配置为响应于掉电状态来迫使数据输出信号路径上的有效逻辑电平。

6. 发明授权

US08358152B2 Integrated circuit including pulse control logic having shared gating control 有权
公开(公告)号：US08358152B2
公开(公告)日：2013-01-22
申请号：US13097206
申请日：2011-04-29
申请人： Edward M. McCombs
发明人： Edward M. McCombs
IPC分类号： H03K19/00
CPC分类号： H03K19/096 , G06F12/1027 , G11C7/062 , Y02D10/13
摘要： An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.

7. 发明申请

US20120124328A1 Translation Lookaside Buffer Structure Including an Output Comparator 有权
标题翻译：包括输出比较器的翻译后备缓冲区结构
公开(公告)号：US20120124328A1
公开(公告)日：2012-05-17
申请号：US13097286
申请日：2011-04-29
申请人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
发明人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
IPC分类号： G06F12/10
CPC分类号： H03K19/096 , G06F12/1027 , G11C7/062 , Y02D10/13
摘要： A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.
摘要翻译：处理器包括包括数据阵列和比较单元的翻译后备缓冲器（TLB）。数据阵列包括多个条目，每个条目被配置为存储相应的翻译的物理地址。响应于对TLB的给定条目的读取访问，数据阵列被配置为在特定时钟周期内输出存储在给定条目中的相应翻译的物理地址。此外，比较单元可以被配置为将由数据阵列输出的相应翻译的物理地址与多个附加地址进行比较。比较单元还可以被配置为为特定时钟周期内的每个附加地址提供命中指示。

8. 发明申请

US20140032201A1 METHOD FOR OPTIMIZING SENSE AMPLIFIER TIMING 审中-公开
标题翻译：优化感应放大器时序的方法
公开(公告)号：US20140032201A1
公开(公告)日：2014-01-30
申请号：US13558976
申请日：2012-07-26
申请人： Edward M. McCombs , Alexander E. Runas , Michael E. Runas
发明人： Edward M. McCombs , Alexander E. Runas , Michael E. Runas
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5045 , G06F2217/10
摘要： Embodiments of a method are disclosed that may allow for the optimization of a memory circuit design parameter. The method may include the statistical simulation of one or more operational parameters of the memory circuit. Probabilities of the operational parameters achieving pre-defined probability goals may be used to optimize the memory circuit design parameter.
摘要翻译：公开了可以允许优化存储器电路设计参数的方法的实施例。该方法可以包括存储器电路的一个或多个操作参数的统计仿真。实现预定义概率目标的操作参数的概率可用于优化存储器电路设计参数。

9. 发明申请

US20130188435A1 MEMORY HAVING ISOLATION UNITS FOR ISOLATING STORAGE ARRAYS FROM A SHARED I/O DURING RETENTION MODE OPERATION 有权
标题翻译：在保留模式操作期间从分享的I / O分离存储阵列的隔离单元的内存
公开(公告)号：US20130188435A1
公开(公告)日：2013-07-25
申请号：US13356786
申请日：2012-01-24
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C5/063 , G11C7/06 , G11C11/4091 , G11C2207/002
摘要： A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
摘要翻译：存储器包括在多个存储阵列之间共享的I / O单元。共享I / O单元提供阵列的输出数据。存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

10. 发明授权

US08493119B2 Scannable flip-flop with hold time improvements 有权
标题翻译：可持续时间改进的可扫描触发器
公开(公告)号：US08493119B2
公开(公告)日：2013-07-23
申请号：US13295992
申请日：2011-11-14
申请人： Derrick A. Leach , Thomas J. Best , Edward M. McCombs
发明人： Derrick A. Leach , Thomas J. Best , Edward M. McCombs
IPC分类号： H03K3/289
CPC分类号： H03K3/35625 , H03K3/012
摘要： Embodiments of a scannable flip-flop are disclosed that may reduce data hold time, which may in turn improve the performance of circuits incorporating the scannable flip-flop. The scannable flip-flop may include a slave latch and a master latch including an input multiplexer. The multiplexer may include a number of input ports, for example to receive normal operating mode data as well as scan operating mode data, and the multiplexer may be operable to controllably select one of the input ports and pass the value of the selected port to an output of the multiplexer. For example, the multiplexer may generate individual control signals for the various ports dependent upon both the clock signal and a select signal, such that each of the ports is qualified with the select signal and the clock signal before the multiplexer presents the input data of the selected port as the output of the multiplexer.
摘要翻译：公开了可扫描触发器的实施例，其可以减少数据保持时间，这又可以提高结合可扫描触发器的电路的性能。可扫描触发器可以包括从锁存器和包括输入多路复用器的主锁存器。复用器可以包括多个输入端口，例如用于接收正常操作模式数据以及扫描操作模式数据，并且多路复用器可操作以可控制地选择输入端口之一并将所选端口的值传递到输出多路复用器。例如，多路复用器可以根据时钟信号和选择信号来生成针对各种端口的各个控制信号，使得每个端口在选择信号和时钟信号之前通过多路复用器提供输入数据选择端口作为多路复用器的输出。

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