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    • 7. 发明授权
    • System and method for handling state change conditions by a program status register
    • 通过程序状态寄存器来处理状态变化的系统和方法
    • US07210051B2
    • 2007-04-24
    • US10703279
    • 2003-11-07
    • Paul J. PatchenWilliam V. Miller
    • Paul J. PatchenWilliam V. Miller
    • G06F1/04
    • G06F9/30101G06F9/3863
    • An improved program status register is disclosed with a feature to handle state change for a processor and its memory subsystem. The program status register comprises a clock, at least one update value for updating the program status register to a second value from a first value when an update enable signal is received, a sampled program status register storing the first value of the program status register, and a state change sampling register generating a synchronized state change signal from a state change indication signal and the clock. When the update enable signal is initially received and a state change indication signal is further received thereafter during a first clock cycle, an updated output of the program status register is restored through a first selection module triggered by the synchronized state change signal to the first value in a second clock cycle following the first clock cycle.
    • 公开了一种改进的程序状态寄存器,其具有处理处理器及其存储器子系统的状态改变的特征。 程序状态寄存器包括时钟,用于当接收到更新使能信号时从第一值将程序状态寄存器更新为第二值的至少一个更新值,存储程序状态寄存器的第一值的采样程序状态寄存器, 以及状态改变采样寄存器,其从状态改变指示信号和时钟产生同步状态改变信号。 当在第一时钟周期中最初接收到更新使能信号并且此后进一步接收状态改变指示信号时,通过由同步状态改变信号触发到第一值的第一选择模块恢复程序状态寄存器的更新输出 在第一个时钟周期之后的第二个时钟周期。
    • 10. 发明申请
    • QUEUE ARBITRATION USING NON-STALLING REQUEST INDICATION
    • 使用非存储请求指示的队列仲裁
    • US20130111090A1
    • 2013-05-02
    • US13286074
    • 2011-10-31
    • William V. MillerChameera R. Fernando
    • William V. MillerChameera R. Fernando
    • G06F13/38
    • G06F13/1663
    • Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.
    • 公开了关于多个主电路和多个目标电路之间的请求仲裁的技术。 在一个实施例中,一种装置包括耦合到目标电路的多个请求队列的仲裁单元。 每个请求队列被配置为存储由多个主电路中的相应一个产生的请求。 仲裁单元被配置为基于指示通过主电路将请求提交给多个请求队列的顺序的信息在多个请求队列中的请求之间进行仲裁。 在一些实施例中,多个主电路中的每一个被配置为向目标电路提供每个请求以指示已经提交了请求的指示,并且仲裁单元被配置为根据请求确定所请求的顺序 就提交的适应症。