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1. 发明授权

US4813002A High speed high density dynamic address translator 失效
标题翻译：高速高密度动态地址转换器
公开(公告)号：US4813002A
公开(公告)日：1989-03-14
申请号：US887768
申请日：1986-07-21
申请人： Thomas F. Joyce , Eugene Nusinov , Richard P. Brown
发明人： Thomas F. Joyce , Eugene Nusinov , Richard P. Brown
IPC分类号： G06F12/10 , G11C15/04 , G11C15/00
CPC分类号： G06F12/1027 , G11C15/04
摘要： A translator is organized to include at least a pair of content addressable memories (CAMs), each for storing a different portion of the total number of bits of each of the words to be translated. The outputs from each CAM are logically combined within a multiple input random access memory (RAM). Both CAMs are interrogated simultaneously and deliver the results of comparing the word portions of an input word and the CAM contents to the RAM in substantially less time then required for a single CAM memory. The results are logically combined with in the RAM which, in response to a match condition, delivers the results of the translation as an output.
摘要翻译：翻译器被组织成包括至少一对内容可寻址存储器（CAM），每个存储器可用于存储要翻译的每个字的总位数的不同部分。每个CAM的输出在逻辑上组合在一个多输入随机存取存储器（RAM）中。两个CAM被同时询问并且将输入字和CAM内容的字部分与RAM相比较的结果，在单个CAM存储器所需要的时间上要少得多。结果在逻辑上与RAM相结合，RAM响应于匹配条件将转换的结果传递为输出。

2. 发明授权

US5053951A Segment descriptor unit for performing static and dynamic address translation operations 失效
标题翻译：用于执行静态和动态地址转换操作的段描述符单元
公开(公告)号：US5053951A
公开(公告)日：1991-10-01
申请号：US331054
申请日：1989-03-28
申请人： Eugene Nusinov , Thomas F. Joyce
发明人： Eugene Nusinov , Thomas F. Joyce
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1036 , G06F12/145 , Y02B60/1225
摘要： A segment descriptor unit (SDU) includes a divided random access memory (RAM), a content addressable memory (CAM) and decoder circuits interconnected for performing dynamic and static address translation operations within a minimum of chip area and power. The CAM is arranged to store a number of entries which include segment number and validity information associated with a corresponding number of segment descriptors. The RAM contains locations allocated for storing segment descriptor words (SDW's) and working data. Each SDW is logically divided into two fields, a static translation word (STW) field containing all of the bits required for performing a static address translation operation and an access control word (ACW) field containing all of the bits required for verifying compliance with system security. The bits of each STW and ACW are stored in alternate bit positions of the SDW locations. Each pair of RAM bit locations couple to a common read/write amplifier and multiplexer circuit. Through the use of microinstruction commands coded to specify different address translation functions, the STW and ACW fields selected by the CAM are read out from RAM during different intervals for carrying out the steps of those operations.
摘要翻译：段描述符单元（SDU）包括分离的随机存取存储器（RAM），内容可寻址存储器（CAM）和互连的解码器电路，用于在最小的芯片面积和功率内执行动态和静态地址转换操作。 CAM被设置为存储多个条目，其包括与相应数量的段描述符相关联的段号和有效性信息。 RAM包含分配用于存储段描述符字（SDW）和工作数据的位置。每个SDW在逻辑上分为两个字段，一个包含执行静态地址转换操作所需的所有位的静态转换字（STW）字段和包含用于验证系统符合性所需的所有位的访问控制字（ACW）字段安全。每个STW和ACW的位被存储在SDW位置的交替位位置。每对RAM位位置耦合到公共读/写放大器和多路复用器电路。通过使用编码的微指令命令来指定不同的地址转换功能，在不同间隔期间，从RAM中选择的STW和ACW字段从RAM中读出，以执行这些操作的步骤。

3. 发明授权

US5430862A Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution 失效
标题翻译：通过RISC指令对CISC指令进行仿真，使用两个流水线级进行重叠的CISC解码和RISC执行
公开(公告)号：US5430862A
公开(公告)日：1995-07-04
申请号：US546348
申请日：1990-06-29
申请人： Steven S. Smith , Arnold J. Smith , Amy E. Gilfeather , Richard P. Brown , Thomas F. Joyce
发明人： Steven S. Smith , Arnold J. Smith , Amy E. Gilfeather , Richard P. Brown , Thomas F. Joyce
IPC分类号： G06F9/318 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/30174 , G06F9/3879
摘要： The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.
摘要翻译：仿真器包括通过双向总线连接的第一和第二流水线级，用于执行通常由高度重叠的方式由不同/源计算机执行的源指令。第一级包括仿真器芯片，其执行取出和解码存储在高速缓冲存储器中的每个源指令的功能，导致生成由第二级执行指令所需的多个向量地址。第二级包括具有片上指令的高性能微处理器芯片和用于存储多个仿真子程序的数据高速缓存和在子程序执行期间取出的数据。以流水线方式，仿真器芯片获取和解码每个源指令，其产生载入分支向量寄存器的向量分支地址，而微处理器芯片从每个先前解码的源获取并执行由总线传送的向量地址指定的仿真子程序指令。

4. 发明授权

US4323967A Local bus interface for controlling information transfers between units in a central subsystem 失效
标题翻译：用于控制中央子系统中单元之间的信息传输的本地总线接口
公开(公告)号：US4323967A
公开(公告)日：1982-04-06
申请号：US140622
申请日：1980-04-15
申请人： Arthur Peters , Virendra S. Negi , David E. Cushing , Richard P. Brown , Thomas F. Joyce
发明人： Arthur Peters , Virendra S. Negi , David E. Cushing , Richard P. Brown , Thomas F. Joyce
IPC分类号： G06F9/46 , G06F12/08 , G06F13/36 , G06F13/364 , G06F13/40 , G06F3/00
CPC分类号： G06F13/364 , G06F12/084 , G06F13/4059
摘要： In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.
摘要翻译：在数据处理系统中，中央子系统包括多个专用处理单元，其中一个处理单元用作中央子系统内的控制处理单元。处理单元耦合到公共子系统总线，用于在中央子系统内传送数据，控制信息和地址信息。子系统总线的访问由总线控制单元分配，总线控制单元还将中央子系统与诸如包括在数据处理系统中的系统存储器或系统I / O设备的其他处理单元接口。

5. 发明授权

US5287522A External procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chip 失效
标题翻译：在RISC芯片中利用内部分支向量中断和向量地址生成的外部过程调用装置
公开(公告)号：US5287522A
公开(公告)日：1994-02-15
申请号：US546347
申请日：1990-06-29
申请人： Richard P. Brown , Thomas F. Joyce , Steven S. Smith
发明人： Richard P. Brown , Thomas F. Joyce , Steven S. Smith
IPC分类号： G06F9/38 , G06F13/24 , G06F13/14 , G06F9/00
CPC分类号： G06F9/3879 , G06F13/24 , G06F9/3861
摘要： A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.
摘要翻译：系统包括通过双向总线互连的第一和第二处理单元。第一处理单元是被编程用于执行存储在片上指令高速缓存单元中的程序的微处理器芯片。第二处理单元从诸如系统总线的外部源接收请求。微处理器芯片包括连接到总线的分支向量设备。第二处理单元响应于外部请求，生成向量分支地址。处理单元将向量分支地址传送到分支向量设备以便存储，同时设置写入指示符。微处理器芯片在检测到写入指示符被设置后，分支到由分支向量地址指定的过程，用于执行该过程的指令以执行处理外部请求或事件所需的那些操作。

6. 发明授权

US4308589A Apparatus for performing the scientific add instruction 失效
标题翻译：用于执行科学添加指令的装置
公开(公告)号：US4308589A
公开(公告)日：1981-12-29
申请号：US93096
申请日：1979-11-08
申请人： Thomas F. Joyce , Richard A. LeMay , William E. Woods , Richard P. Brown
发明人： Thomas F. Joyce , Richard A. LeMay , William E. Woods , Richard P. Brown
IPC分类号： G06F9/302 , G06F7/50
CPC分类号： G06F9/30014 , G06F9/30036
摘要： The performance of a scientific ADD instruction is improved by storing the mantissas of both operands in each of two random access memories, selecting the mantissa with the smaller exponent, shifting that mantissa and performing the ADD operation of adding the mantissas in one machine cycle.
摘要翻译：通过将两个操作数的尾数存储在两个随机存取存储器中的每一个中，选择具有较小指数的尾数，移动该尾数并执行在一个机器周期中添加尾数的ADD操作来改进科学ADD指令的性能。

7. 发明授权

US6125436A Symmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address space 失效
标题翻译：具有统一环境和分布式系统功能的对称多处理系统，其中总线操作相关的存储空间映射到单个系统地址空间
公开(公告)号：US6125436A
公开(公告)日：2000-09-26
申请号：US855810
申请日：1997-05-12
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F. Joyce , Martin Massucci , Lance J. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F12/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
摘要翻译：具有统一环境和分布式系统功能的对称多处理系统为系统中的所有功能单元提供统一的地址空间，同时在系统的功能单元上分配各种系统功能的执行，每个功能单元承担其自身方面的责任操作。此外，该系统提供改进的系统总线操作，用于从存储器传输数据。

8. 发明授权

US5283870A Method and apparatus for avoiding processor deadly embrace in a multiprocessor system 失效
标题翻译：用于在多处理器系统中避免处理器致命包围的方法和装置
公开(公告)号：US5283870A
公开(公告)日：1994-02-01
申请号：US771296
申请日：1991-10-04
申请人： Thomas F. Joyce , James W. Keeley
发明人： Thomas F. Joyce , James W. Keeley
IPC分类号： G06F9/46 , G06F15/167 , G06F13/14
CPC分类号： G06F9/524 , G06F15/167
摘要： A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.
摘要翻译：多处理器系统包括许多系统处理器，其紧密耦合到系统总线以共享主或系统存储器以及还紧密耦合到系统总线的多个板载存储器处理器。每个处理器都有一个高性能微处理器，通过微处理器的本地总线紧密耦合到板载或本地存储器。使用内存锁定协议访问系统内存，而本地内存可通过总线锁定协议访问。每个板上存储器处理器包括锁机构，其能够处理针对其本地存储器的存储器锁定命令，该存储器锁定命令经由系统总线从任何其他处理器接收并用于向系统存储器发出存储器锁定命令。

9. 发明授权

US5193181A Recovery method and apparatus for a pipelined processing unit of a multiprocessor system 失效
标题翻译：多处理器系统管道处理单元的恢复方法和装置
公开(公告)号：US5193181A
公开(公告)日：1993-03-09
申请号：US593458
申请日：1990-10-05
申请人： George J. Barlow , James W. Keeley , Richard A. Lemay , Jian-Kuo Shen , Robert V. Ledoux, deceased , Thomas F. Joyce , Richard P. Kelly , Robert C. Miller
发明人： George J. Barlow , James W. Keeley , Richard A. Lemay , Jian-Kuo Shen , Robert V. Ledoux, deceased , Thomas F. Joyce , Richard P. Kelly , Robert C. Miller
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/0766 , G06F11/004 , G06F11/2205
摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

10. 发明授权

US5148533A Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units 失效
标题翻译：在具有多个执行和数据高速缓存单元的紧密耦合的数据处理系统中的数据组一致性的装置和方法
公开(公告)号：US5148533A
公开(公告)日：1992-09-15
申请号：US294534
申请日：1989-01-05
申请人： Thomas F. Joyce , Robert C. Miller , Marc C. Vogt
发明人： Thomas F. Joyce , Robert C. Miller , Marc C. Vogt
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： In a data processing system having a plurality of tightly coupled data processing units connected by an asynchronous system bus, apparatus and an associated method are described for maintaining the coherency of data groups stored in instruction cache units and execution cache units. The apparatus includes a monitor unit as part of the bus interface unit, and a bus interface unit coupling each associated data processing unit to the system bus. The monitor unit receives signals, applied to the system bus, identifying data groups transferred between the memory unit and the data processing units, including those data groups originating from the bus interface unit of which the monitor unit is a component. The bus interface unit includes directories duplicating the contents of the instruction cache unit directory and the execution cache unit directory. The monitor unit, in response to signals applied to the system bus, identifies operations that can compromise the integrity of signals stored in the associated data processing unit. The monitor unit accesses the appropriate duplicate directory to determine if the address of a compromised data group validly exists in the duplicate directory. When an address is stored in the duplicate directory along with a valid signal, the valid signal is removed from both the cache directory and the duplicate directory.
摘要翻译：在具有通过异步系统总线连接的多个紧密耦合的数据处理单元的数据处理系统中，描述了用于维持存储在指令高速缓存单元和执行高速缓存单元中的数据组的一致性的装置和相关联的方法。该装置包括作为总线接口单元的一部分的监视器单元和将每个相关联的数据处理单元耦合到系统总线的总线接口单元。监视器单元接收施加到系统总线的信号，识别在存储器单元和数据处理单元之间传送的数据组，包括源自监视器单元是组件的总线接口单元的那些数据组。总线接口单元包括复制指令高速缓存单元目录和执行高速缓存单元目录的内容的目录。监视器单元响应于施加到系统总线的信号来识别可能危及存储在相关联的数据处理单元中的信号的完整性的操作。监视器单元访问适当的重复目录，以确定受损数据组的地址是否有效存在于重复目录中。当地址与有效信号一起存储在重复目录中时，有效信号将从缓存目录和重复目录中移除。

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