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    • 2. 发明授权
    • Segment descriptor unit for performing static and dynamic address
translation operations
    • 用于执行静态和动态地址转换操作的段描述符单元
    • US5053951A
    • 1991-10-01
    • US331054
    • 1989-03-28
    • Eugene NusinovThomas F. Joyce
    • Eugene NusinovThomas F. Joyce
    • G06F12/10G06F12/14
    • G06F12/1036G06F12/145Y02B60/1225
    • A segment descriptor unit (SDU) includes a divided random access memory (RAM), a content addressable memory (CAM) and decoder circuits interconnected for performing dynamic and static address translation operations within a minimum of chip area and power. The CAM is arranged to store a number of entries which include segment number and validity information associated with a corresponding number of segment descriptors. The RAM contains locations allocated for storing segment descriptor words (SDW's) and working data. Each SDW is logically divided into two fields, a static translation word (STW) field containing all of the bits required for performing a static address translation operation and an access control word (ACW) field containing all of the bits required for verifying compliance with system security. The bits of each STW and ACW are stored in alternate bit positions of the SDW locations. Each pair of RAM bit locations couple to a common read/write amplifier and multiplexer circuit. Through the use of microinstruction commands coded to specify different address translation functions, the STW and ACW fields selected by the CAM are read out from RAM during different intervals for carrying out the steps of those operations.
    • 段描述符单元(SDU)包括分离的随机存取存储器(RAM),内容可寻址存储器(CAM)和互连的解码器电路,用于在最小的芯片面积和功率内执行动态和静态地址转换操作。 CAM被设置为存储多个条目,其包括与相应数量的段描述符相关联的段号和有效性信息。 RAM包含分配用于存储段描述符字(SDW)和工作数据的位置。 每个SDW在逻辑上分为两个字段,一个包含执行静态地址转换操作所需的所有位的静态转换字(STW)字段和包含用于验证系统符合性所需的所有位的访问控制字(ACW)字段 安全。 每个STW和ACW的位被存储在SDW位置的交替位位置。 每对RAM位位置耦合到公共读/写放大器和多路复用器电路。 通过使用编码的微指令命令来指定不同的地址转换功能,在不同间隔期间,从RAM中选择的STW和ACW字段从RAM中读出,以执行这些操作的步骤。
    • 3. 发明授权
    • LSI microprocessor chip with backward pin compatibility
    • LSI微处理器芯片具有向后引脚兼容性
    • US4654789A
    • 1987-03-31
    • US596756
    • 1984-04-04
    • Eugene NusinovJohn J. Bradley
    • Eugene NusinovJohn J. Bradley
    • G06F1/22G06F12/06G06F1/00G06F13/00
    • G06F12/0623G06F1/22H01L2924/0002
    • A chip implemented in newer technology is designed to include new functionality. The chip includes compatibility circuits which connect to a pin which is unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at higher speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with the new functionality at the same higher speed and improved performance as compared to the replaced chip.
    • 以较新技术实现的芯片旨在包括新功能。 该芯片包括连接到在现有计算机系统中替代的芯片中未使用的引脚的兼容性电路。 兼容性电路连接到包含新添加或改变的功能的新芯片的内部部分。 新芯片就像以前的芯片一样安装在现有的计算机系统中。 当这样安装时,兼容性电路使新芯片能够以与更换的芯片相同的方式工作,但是以更高的速度和更好的性能。 当新芯片安装在其设计的系统中时,兼容性电路使得芯片能够以与更换的芯片相同的更高速度和更高的性能与新的功能一起运行。