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1. 发明授权

US5430862A Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution 失效
标题翻译：通过RISC指令对CISC指令进行仿真，使用两个流水线级进行重叠的CISC解码和RISC执行
公开(公告)号：US5430862A
公开(公告)日：1995-07-04
申请号：US546348
申请日：1990-06-29
申请人： Steven S. Smith , Arnold J. Smith , Amy E. Gilfeather , Richard P. Brown , Thomas F. Joyce
发明人： Steven S. Smith , Arnold J. Smith , Amy E. Gilfeather , Richard P. Brown , Thomas F. Joyce
IPC分类号： G06F9/318 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/30174 , G06F9/3879
摘要： The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.
摘要翻译：仿真器包括通过双向总线连接的第一和第二流水线级，用于执行通常由高度重叠的方式由不同/源计算机执行的源指令。第一级包括仿真器芯片，其执行取出和解码存储在高速缓冲存储器中的每个源指令的功能，导致生成由第二级执行指令所需的多个向量地址。第二级包括具有片上指令的高性能微处理器芯片和用于存储多个仿真子程序的数据高速缓存和在子程序执行期间取出的数据。以流水线方式，仿真器芯片获取和解码每个源指令，其产生载入分支向量寄存器的向量分支地址，而微处理器芯片从每个先前解码的源获取并执行由总线传送的向量地址指定的仿真子程序指令。

2. 发明授权

US4992930A Synchronous cache memory system incorporating tie-breaker apparatus for maintaining cache coherency using a duplicate directory 失效
标题翻译：同步缓存存储器系统，其中包含用于使用重复目录维持高速缓存一致性的联合断路器装置
公开(公告)号：US4992930A
公开(公告)日：1991-02-12
申请号：US191319
申请日：1988-05-09
申请人： Amy E. Gilfeather , George J. Barlow
发明人： Amy E. Gilfeather , George J. Barlow
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system includes a processing unit which, together with other processing units, including input/output units, connects in common to an asynchronous bus network for sharing a main memory. At least one processing unit includes a synchronous private write through cache memory system which includes a main directory and data store in addition to a bus watcher and a duplicate directory. The bus watcher connects to the asynchronous bus network and captures all main memory requests while the duplicate directory maintains a copy of the cache unit's main directory. Independently and autonomously synchronously operated tie-breaker circuits apply requests to the main and duplicate directories. When tie-breaker circuits detect conditions relating to a request which could result in cache incoherency, it initiates uninterrupted sequences of cycles within the corresponding cache main or duplicate directory to complete the processing of that same request.
摘要翻译：多处理器数据处理系统包括处理单元，其与包括输入/输出单元的其它处理单元一起共同连接到用于共享主存储器的异步总线网络。至少一个处理单元包括除了总线监视器和复制目录之外还包括主目录和数据存储器的通过高速缓存存储器系统的同步专用写入。总线监视器连接到异步总线网络并捕获所有主存储器请求，而重复目录保存缓存单元的主目录的副本。独立和自主地同步操作的断路器电路将请求应用于主和重复目录。当断路器电路检测到可能导致高速缓存不相容性的请求的条件时，它会在相应的缓存主目录或重复目录中启动不间断的周期序列，以完成同一请求的处理。

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