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1. 发明申请

US20080111202A1 FORMING CONDUCTIVE STUD FOR SEMICONDUCTIVE DEVICES 有权
公开(公告)号：US20080111202A1
公开(公告)日：2008-05-15
申请号：US12013622
申请日：2008-01-14
申请人： Thomas Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L29/78
CPC分类号： H01L21/823871 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

2. 发明申请

US20070254420A1 SOURCE/DRAIN IMPLANTATION AND CHANNEL STRAIN TRANSFER USING DIFFERENT SIZED SPACERS AND RELATED SEMICONDUCTOR DEVICE 审中-公开
标题翻译：使用不同尺寸的间距和相关半导体器件的源/漏极植入和通道应变传输
公开(公告)号：US20070254420A1
公开(公告)日：2007-11-01
申请号：US11380743
申请日：2006-04-28
申请人： Atul Ajmera , Christopher Baiocco , Xiangdong Chen , Thomas Dyer , Sunfei Fang , Wenzhi Gao
发明人： Atul Ajmera , Christopher Baiocco , Xiangdong Chen , Thomas Dyer , Sunfei Fang , Wenzhi Gao
IPC分类号： H01L21/338 , H01L21/20 , H01L29/76
CPC分类号： H01L21/823425 , H01L21/823412 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： Methods for source/drain implantation and strain transfer to a channel of a semiconductor device and a related semiconductor device are disclosed. In one embodiment, the method includes using a first size spacer for deep source/drain implantation adjacent a gate region of a semiconductor device; and using a second, smaller size spacer for silicide formation adjacent the gate region and transferring strain from a stress liner to a channel underlying the gate region. One embodiment of a semiconductor device may include a gate region atop a substrate; a spacer including a spacer core and an outer spacer member about the spacer core; a deep source/drain region within the substrate and distanced from the spacer; and a silicide region within the substrate and overlapping and extending beyond the deep source/drain region, the silicide region aligned to the spacer.
摘要翻译：公开了用于源极/漏极注入和应变转移到半导体器件和相关半导体器件的沟道的方法。在一个实施例中，该方法包括使用与半导体器件的栅极区域相邻的深源极/漏极注入的第一尺寸间隔物; 并且使用第二较小尺寸的间隔物，用于邻近栅极区域的硅化物形成，并将应变从应力衬垫转移到栅极区域下方的沟道。半导体器件的一个实施例可以包括位于衬底顶部的栅极区域; 间隔件，其包括间隔件芯和围绕所述间隔件芯的外部间隔件; 衬底内的深源极/漏极区域，并远离间隔物; 以及衬底内的硅化物区域，并且重叠并延伸超过深源极/漏极区域，硅化物区域与间隔物对准。

3. 发明授权

US07585773B2 Non-conformal stress liner for enhanced MOSFET performance 失效
标题翻译：非保形应力衬垫，用于增强MOSFET性能
公开(公告)号：US07585773B2
公开(公告)日：2009-09-08
申请号：US11556591
申请日：2006-11-03
申请人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
发明人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
IPC分类号： H01L29/72
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.
摘要翻译：提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。本发明是针对制造所述半导体器件的方法。

4. 发明申请

US20080122003A1 NON-CONFORMAL STRESS LINER FOR ENHANCED MOSFET PERFORMANCE 失效
标题翻译：非稳定应力衬管，用于增强MOSFET性能
公开(公告)号：US20080122003A1
公开(公告)日：2008-05-29
申请号：US11556591
申请日：2006-11-03
申请人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
发明人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
IPC分类号： H01L27/092 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.
摘要翻译：提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。本发明是针对制造所述半导体器件的方法。

5. 发明申请

US20070194387A1 EXTENDED RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED CONTACT AREA AND METHOD FOR FORMING EXTENDED RAISED SOURCE/DRAIN STRUCTURE 有权
标题翻译：用于增强接触区域的扩展源/排水结构和形成扩展源/排水结构的方法
公开(公告)号：US20070194387A1
公开(公告)日：2007-08-23
申请号：US11307759
申请日：2006-02-21
申请人： Thomas Dyer , Sunfei Fang
发明人： Thomas Dyer , Sunfei Fang
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L21/823814 , H01L21/823418 , H01L21/823425 , H01L21/823475 , H01L21/823871 , H01L29/517 , H01L29/66628 , H01L29/7834
摘要： A semiconductor device comprises a gate electrode stack having sidewalls and a top surface with a gate dielectric layer and the gate electrode, and LDD/LDS regions in the substrate aligned with the stack. Conformal L-shaped etch-stop layers with a thickness from about 50 Å to about 200 Å are formed with a vertical leg on the sidewalls of the stack and a horizontal leg reaching over the LDD/LDS regions next to the stack. RSD regions are formed in contact with the substrate aside from the etch-stop layers. The RSD regions cover the horizontal leg of the etch-stop layer and cover at least a portion of the vertical leg of the etch-stop layer on the sidewall of the gate electrode.
摘要翻译：半导体器件包括具有侧壁的栅极电极堆叠和具有栅极电介质层和栅电极的顶表面，并且衬底中的LDD / LDS区域与堆叠对准。形成厚度为约至约200的保形L形蚀刻停止层，其在堆叠的侧壁上具有垂直支腿，并且在堆叠旁边的LDD / LDS区域上形成水平支线。除了蚀刻停止层之外，RSD区域与基板形成接触。 RSD区域覆盖蚀刻停止层的水平支腿并且覆盖栅电极的侧壁上的蚀刻停止层的垂直支腿的至少一部分。

6. 发明申请

US20070141936A1 Dispersible wet wipes with improved dispensing 审中-公开
标题翻译：可分散的湿抹布，具有改进的分配
公开(公告)号：US20070141936A1
公开(公告)日：2007-06-21
申请号：US11300967
申请日：2005-12-15
申请人： William Bunyard , Kelly Branham , Michael Lostocco , Thomas Dyer , Jeffrey Hockersmith , Kevin Possell
发明人： William Bunyard , Kelly Branham , Michael Lostocco , Thomas Dyer , Jeffrey Hockersmith , Kevin Possell
IPC分类号： B32B27/04 , B32B27/12 , B32B5/02
CPC分类号： A61L15/62 , D04H1/587 , D04H1/64 , Y10T442/2508 , Y10T442/2525 , Y10T442/2738 , Y10T442/60
摘要： The present invention provides a wet wipe with improved sheet-to-sheet adhesion properties. The wet wipe comprises a non-woven web saturated with a wetting composition. In another embodiment, the wet wipe comprises a non-woven web with an anti-blocking composition.
摘要翻译：本发明提供具有改进的片对粘合性能的湿巾。湿巾包括用润湿组合物饱和的无纺网。在另一个实施方案中，湿擦巾包括具有防粘连组合物的无纺网。

7. 发明申请

US20060199320A1 METHOD FOR FORMING SELF-ALIGNED, DUAL SILICON NITRIDE LINER FOR CMOS DEVICES 失效
标题翻译：用于形成用于CMOS器件的自对准的双硅氮化物衬底的方法
公开(公告)号：US20060199320A1
公开(公告)日：2006-09-07
申请号：US10906670
申请日：2005-03-01
申请人： Thomas Dyer , Haining Yang
发明人： Thomas Dyer , Haining Yang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/7843
摘要： A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and forming a topographic layer over the first type nitride layer. Portions of the first type nitride layer and the topographic layer over the second polarity type device are patterned and removed. A second type nitride layer is formed over the second polarity type device, and over remaining portions of the topographic layer over the first polarity type device so as to define a vertical pillar of second type nitride material along a sidewall of the topographic layer, the second type nitride layer in contact with a sidewall of the first type nitride layer. The topographic layer is removed and the vertical pillar is removed.
摘要翻译：用于形成用于CMOS器件的自对准双氮化硅衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一氮化物层，并在第一氮化物层上形成形貌层。第一类型氮化物层和第二极性类型器件上的形貌层的部分被图案化和去除。在第二极性类型器件上形成第二类型氮化物层，并且在第一极性类型器件上方形成地形层的剩余部分，以沿着地形层的侧壁限定第二类型氮化物材料的垂直柱，第二氮化物层与第一氮化物层的侧壁接触。去除地形层并移除垂直柱。

8. 发明申请

US20060144536A1 Soft and durable tissues made with thermoplastic polymer complexes 审中-公开
标题翻译：用热塑性聚合物复合物制成的柔软耐用的纸巾
公开(公告)号：US20060144536A1
公开(公告)日：2006-07-06
申请号：US11027065
申请日：2004-12-30
申请人： Deborah Nickel , Troy Runge , Gil Bernard Garnier , Thomas Dyer
发明人： Deborah Nickel , Troy Runge , Gil Bernard Garnier , Thomas Dyer
IPC分类号： B31F1/12 , D21H17/36
CPC分类号： D21H27/002 , D21H17/35 , D21H17/36 , D21H17/37 , D21H21/24
摘要： A thermoplastic complex comprises an emulsified hydrophobic thermoplastic polymer and a complexing agent. The thermoplastic complex can formed by pre-mixing an emulsified hydrophobic thermoplastic polymer with a complexing agent to form a paste-like complex. The thermoplastic complex can then be dispersed in a water-fiber suspension in the wet-end section of a tissuemaking process. The fibers in the water-fiber suspension retain a substantial amount of the complex. A fibrous web can be formed comprising the treated fibers, which can then be converted into a tissue product that exhibits improved softness with minimized slough.
摘要翻译：热塑性复合物包括乳化的疏水性热塑性聚合物和络合剂。热塑性复合物可以通过将乳化的疏水性热塑性聚合物与络合剂预混合形成糊状复合物而形成。然后将热塑性复合物分散在组织工艺的湿端部分的水纤维悬浮液中。水纤维悬浮液中的纤维保留了大量的复合物。可以形成包含经处理的纤维的纤维网，然后可以将其转化为以最小化的松弛表现出改善的柔软性的组织产品。

9. 发明申请

US20080305621A1 CHANNEL STRAIN ENGINEERING IN FIELD-EFFECT-TRANSISTOR 有权
标题翻译：场效应晶体管中的通道应变工程
公开(公告)号：US20080305621A1
公开(公告)日：2008-12-11
申请号：US11760056
申请日：2007-06-08
申请人： Thomas Dyer , Rajendran Krishnasamy , Jin-Ping Han , Ernst Demm
发明人： Thomas Dyer , Rajendran Krishnasamy , Jin-Ping Han , Ernst Demm
IPC分类号： H01L21/3205
CPC分类号： H01L29/7845 , H01L21/28026 , H01L21/28079 , H01L21/823807 , H01L29/165 , H01L29/49 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.
摘要翻译：公开了一种对包括栅极，源极区和漏极区的场效应晶体管的栅极下面的沟道区域施加应力的方法。该方法包括以下步骤：将应力源嵌入在FET的源极和漏极区域中; 形成覆盖所述栅极和所述源极和漏极区域的应力衬垫; 去除所述应力衬垫的一部分，所述应力衬垫的所述部分位于所述FET的栅极顶部; 去除第一栅极材料的栅极的至少大部分，从而在其中形成开口; 并用第二栅极材料填充开口。

10. 发明授权

US07442614B1 Silicon on insulator devices having body-tied-to-source and methods of making 失效
标题翻译：硅绝缘体器件具有身体束缚源和制造方法
公开(公告)号：US07442614B1
公开(公告)日：2008-10-28
申请号：US12052807
申请日：2008-03-21
申请人： Thomas Dyer , Jack A. Mandelman , Keith Kwong Hon Wong , Chih-Chao Yang , Haining Sam Yang
发明人： Thomas Dyer , Jack A. Mandelman , Keith Kwong Hon Wong , Chih-Chao Yang , Haining Sam Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/7835 , H01L29/78618
摘要： Methods of fabricating silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a method of forming a transistor device comprises: providing a semiconductor topography comprising a gate conductor spaced above a semiconductor layer by a gate dielectric, dielectric sidewall spacers adjacent to sidewalls of the gate conductor, and source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and implanting metallic species in a bottom region of the semiconductor layer to form a conductive implant region to electrically connect the source junction to the body region.
摘要翻译：描述了具有身体绑定到源的绝缘体上的硅的制造方法。在一个实施例中，一种形成晶体管器件的方法包括：提供包括通过栅极电介质在半导体层之上间隔开的栅极导体的半导体形貌，与栅极导体的侧壁相邻的电介质侧壁间隔和横向间隔开的源极和漏极结通过半导体层中的体区; 以及将所述金属物质植入所述半导体层的底部区域中以形成导电注入区域，以将所述源极结电连接到所述身体区域。

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