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1. 发明申请

US20090108374A1 HIGH DENSITY SRAM CELL WITH HYBRID DEVICES 有权
标题翻译：高密度SRAM单元与混合器件
公开(公告)号：US20090108374A1
公开(公告)日：2009-04-30
申请号：US11928418
申请日：2007-10-30
申请人： Robert C. Wong , Haining Sam Yang
发明人： Robert C. Wong , Haining Sam Yang
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/1104 , H01L27/11
摘要： Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-up devices of the inverters and the pass gate devices are planar FETs or pull-down and pull-up devices of the inverters are FinFETs while the pass gate devices are planar FETs.
摘要翻译：混合SRAM电路，混合SRAM结构和制造混合SRAM的方法。 SRAM结构包括耦合到第一和第二通道栅极器件的第一和第二交叉耦合反相器。逆变器的下拉器件是FinFET，而反相器的上拉器件和通栅器件是平面FET，反相器的下拉和上拉器件是FinFET，而栅极器件是平面FET。

2. 发明授权

US07955952B2 Crackstop structures and methods of making same 有权
标题翻译：裂缝结构及其制作方法
公开(公告)号：US07955952B2
公开(公告)日：2011-06-07
申请号：US12174994
申请日：2008-07-17
申请人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
发明人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L23/585 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate.
摘要翻译：集成电路芯片和制造集成电路芯片的方法。集成电路芯片包括：接近集成电路芯片的周边的连续的第一应力环，第一应力环的相应边缘平行于集成电路芯片的相应边缘; 所述第一应力环与所述集成电路芯片的周边之间的连续的第二应力环，所述第二应力环平行于所述集成电路芯片的相应边缘的相应边缘，所述第一和第二应力环具有相反的内应力; 第一应力环和第二应力环之间的连续间隙; 以及从基板上的第一布线电平到最后布线电平的一组布线电平。

3. 发明授权

US07545034B2 Thermal energy removal structure and method 有权
标题翻译：热能消除结构与方法
公开(公告)号：US07545034B2
公开(公告)日：2009-06-09
申请号：US11767850
申请日：2007-06-25
申请人： Deok-kee Kim , Wai-Kin Li , Haining Sam Yang
发明人： Deok-kee Kim , Wai-Kin Li , Haining Sam Yang
IPC分类号： H01L23/34
CPC分类号： H05K7/205 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： An electrical structure including a first substrate comprising a plurality of electrical components, a first thermally conductive film layer formed over and in contact with a first electrical component of the plurality of electrical components, a first thermally conductive structure in mechanical contact with a first portion of the first thermally conductive film layer, and a first thermal energy extraction structure formed over the first thermally conductive structure. The first thermal energy extraction structure is in thermal contact with the first thermally conductive structure. The first thermal energy extraction structure is configured to extract a first portion of thermal energy from the first electrical component through the first thermally conductive film layer and the first thermally conductive structure.
摘要翻译：一种电气结构，包括包括多个电气部件的第一基板，形成在所述多个电气部件中的第一电气部件上并与之接触的第一导热膜层，与所述多个电气部件的第一部分机械接触的第一导热结构第一导热膜层和形成在第一导热结构上的第一热能提取结构。第一热能提取结构与第一导热结构热接触。第一热能提取结构被配置为从第一电气部件通过第一导热膜层和第一导热结构提取热能的第一部分。

4. 发明申请

US20090090994A1 ELECTROMIGRATION FUSE AND METHOD OF FABRICATING SAME 有权
标题翻译：电磁保险丝及其制造方法
公开(公告)号：US20090090994A1
公开(公告)日：2009-04-09
申请号：US11869227
申请日：2007-10-09
申请人： Deok-kee Kim , Haining Sam Yang
发明人： Deok-kee Kim , Haining Sam Yang
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer.
摘要翻译：保险丝和形成保险丝的方法。保险丝包括：半导体衬底上的电介质层; 电介质层上的阴极堆叠，阴极堆叠的侧壁从阴极堆叠的顶表面延伸到电介质层的顶表面; 连续多晶硅层，包括阴极区域，阳极区域，阴极和阳极区域之间的连接区域以及阴极区域和连接区域之间的过渡区域，靠近阴极堆叠侧壁的过渡区域，阴极区域在阴极堆叠的顶表面上，电介质层的顶表面上的连接区域，阴极区域的第一厚度和连接区域的第二厚度大于过渡区域的第三厚度; 以及在所述多晶硅层的顶表面上的金属硅化物层。

5. 发明申请

US20080316709A1 Thermally Conductive Electrical Structure and Method 有权
标题翻译：导电电气结构与方法
公开(公告)号：US20080316709A1
公开(公告)日：2008-12-25
申请号：US11767850
申请日：2007-06-25
申请人： Deok-kee Kim , Wai-Kin Li , Haining Sam Yang
发明人： Deok-kee Kim , Wai-Kin Li , Haining Sam Yang
IPC分类号： H05K7/20
CPC分类号： H05K7/205 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： An electrical structure and method of forming. The electrical structure includes a first substrate comprising a plurality of electrical components, a first thermally conductive film layer formed over and in contact with a first electrical component of the plurality of electrical components, a first thermally conductive structure in mechanical contact with a first portion of the first thermally conductive film layer, and a first thermal energy extraction structure formed over the first thermally conductive structure. The first thermal energy extraction structure is in thermal contact with the first thermally conductive structure. The first thermal energy extraction structure is configured to extract a first portion of thermal energy from the first electrical component through the first thermally conductive film layer and the first thermally conductive structure.
摘要翻译：一种电气结构和成型方法。电结构包括包括多个电气部件的第一基板，形成在多个电气部件中的第一电气部件上并与其接触的第一导热膜层，与第一部分的第一部分机械接触的第一导热结构第一导热膜层和形成在第一导热结构上的第一热能提取结构。第一热能提取结构与第一导热结构热接触。第一热能提取结构被配置为从第一电气部件通过第一导热膜层和第一导热结构提取热能的第一部分。

6. 发明授权

US07790542B2 CMOS devices having reduced threshold voltage variations and methods of manufacture thereof 失效
标题翻译：具有降低的阈值电压变化的CMOS器件及其制造方法
公开(公告)号：US07790542B2
公开(公告)日：2010-09-07
申请号：US12141314
申请日：2008-06-18
申请人： Thomas Walter Dyer , Haining Sam Yang
发明人： Thomas Walter Dyer , Haining Sam Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/823842 , H01L21/764 , H01L21/823864 , H01L21/823871 , H01L29/4966 , H01L29/517
摘要： Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.
摘要翻译：提供了应力增强型晶体管器件及其制造方法。在一个实施例中，晶体管器件包括：栅极导体，设置在一对电介质间隔物之间的半导体衬底之上，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，区域覆盖电介质间隔物以形成通道区域的底切区域; 以及设置在半导体衬底的凹陷区域中的外延源极和漏极区域，并且在电介质间隔物的下方横向延伸到沟道区域的底切区域中。

7. 发明授权

US07709928B2 Electromigration fuse and method of fabricating same 有权
标题翻译：电流保险丝及其制造方法
公开(公告)号：US07709928B2
公开(公告)日：2010-05-04
申请号：US11869227
申请日：2007-10-09
申请人： Deok-kee Kim , Haining Sam Yang
发明人： Deok-kee Kim , Haining Sam Yang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer.
摘要翻译：保险丝和形成保险丝的方法。保险丝包括：半导体衬底上的电介质层; 电介质层上的阴极堆叠，阴极堆叠的侧壁从阴极堆叠的顶表面延伸到电介质层的顶表面; 连续多晶硅层，包括阴极区域，阳极区域，阴极和阳极区域之间的连接区域以及阴极区域和连接区域之间的过渡区域，靠近阴极堆叠侧壁的过渡区域，阴极区域在阴极堆叠的顶表面上，电介质层的顶表面上的连接区域，阴极区域的第一厚度和连接区域的第二厚度大于过渡区域的第三厚度; 以及在所述多晶硅层的顶表面上的金属硅化物层。

8. 发明申请

US20100012950A1 CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME 失效
标题翻译： CRACKSTOP结构及其制造方法
公开(公告)号：US20100012950A1
公开(公告)日：2010-01-21
申请号：US12175006
申请日：2008-07-17
申请人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
发明人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
IPC分类号： H01L29/15 , H01L21/76
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop.
摘要翻译：集成电路芯片和制造集成电路芯片的方法。集成电路芯片包括：从第一布线电平堆叠到最后布线电平的一组布线电平; 以及设定布线层的两个或多个布线层次的每个布线层中的相应空隙，每个相应的空隙以连续的环平行并靠近集成电路芯片的周边延伸，直接堆叠在较高布线层上的空隙但是不接触下部布线层的空隙，各个空隙形成裂纹停止。

9. 发明授权

US07915691B2 High density SRAM cell with hybrid devices 有权
标题翻译：具有混合器件的高密度SRAM单元
公开(公告)号：US07915691B2
公开(公告)日：2011-03-29
申请号：US11928418
申请日：2007-10-30
申请人： Robert C. Wong , Haining Sam Yang
发明人： Robert C. Wong , Haining Sam Yang
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/11
摘要： Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-up devices of the inverters and the pass gate devices are planar FETs or pull-down and pull-up devices of the inverters are FinFETs while the pass gate devices are planar FETs.
摘要翻译：混合SRAM电路，混合SRAM结构和制造混合SRAM的方法。 SRAM结构包括耦合到第一和第二通道栅极器件的第一和第二交叉耦合反相器。逆变器的下拉器件是FinFET，而反相器的上拉器件和通栅器件是平面FET，反相器的下拉和上拉器件是FinFET，而栅极器件是平面FET。

10. 发明申请

US20100013043A1 CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME 有权
标题翻译： CRACKSTOP结构及其制造方法
公开(公告)号：US20100013043A1
公开(公告)日：2010-01-21
申请号：US12174994
申请日：2008-07-17
申请人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
发明人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L23/585 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate.
摘要翻译：集成电路芯片和制造集成电路芯片的方法。集成电路芯片包括：接近集成电路芯片的周边的连续的第一应力环，第一应力环的相应边缘平行于集成电路芯片的相应边缘; 所述第一应力环与所述集成电路芯片的周边之间的连续的第二应力环，所述第二应力环平行于所述集成电路芯片的相应边缘的相应边缘，所述第一和第二应力环具有相反的内应力; 第一应力环和第二应力环之间的连续间隙; 以及从基板上的第一布线电平到最后布线电平的一组布线电平。

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