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1. 发明申请

US20150180799A1 HIERARCHICAL/LOSSLESS PACKET PREEMPTION TO REDUCE LATENCY JITTER IN FLOW-CONTROLLED PACKET-BASED NETWORKS 审中-公开
标题翻译：基于分组的网络中的分层/不可信分组预防措施来减少延迟抖动
公开(公告)号：US20150180799A1
公开(公告)日：2015-06-25
申请号：US14136293
申请日：2013-12-20
申请人： Thomas D. Lovett , Albert Cheng , Mark S. Birrittella , James Kunz , Todd Rimmer
发明人： Thomas D. Lovett , Albert Cheng , Mark S. Birrittella , James Kunz , Todd Rimmer
IPC分类号： H04L12/911 , H04L12/851 , H04L1/00
CPC分类号： H04L47/821 , H04L1/0041 , H04L1/0061 , H04L1/0071 , H04L1/1835 , H04L25/14 , H04L47/2441 , H04L47/365 , H04L47/621 , H04L47/6275
摘要： Methods, apparatus, and systems for implementing hierarchical and lossless packet preemption and interleaving to reduce latency jitter in flow-controller packet-based networks. Fabric packets are divided into a plurality of data units, with data units for different fabric packets buffered in separate buffers. Data units are pulled from the buffers and added to a transmit stream in which groups of data units are interleaved. Upon receipt by a receiver, the groups of data units are separated out and buffered in separate buffers under which data units for the same fabric packets are grouped together. In one aspect, each buffer is associated with a respective virtual lane (VL), and the fabric packets are effectively transferred over fabric links using virtual lanes. VLs may have different levels of priority under which data units for fabric packets in higher-priority VLs may preempt fabric packets in lower-priority VLs. By transferring data units rather than entire packets, transmission of a packet can be temporarily paused in favor of a higher-priority packet. Multiple levels of preemption and interleaving in a nested manner are supported.
摘要翻译：用于实现分级和无损数据包抢占和交织以减少流控制器基于分组的网络中的延迟抖动的方法，装置和系统。结构数据包被划分为多个数据单元，不同结构数据包的数据单元缓冲在单独的缓冲区中。数据单元被从缓冲器中拉出并且被添加到数据单元组交错的发送流中。在由接收器接收时，数据单元组被分离出并且在单独的缓冲器中缓冲，在这些缓冲器中，用于相同结构数据包的数据单元被分组在一起。在一个方面，每个缓冲器与相应的虚拟通道（VL）相关联，并且使用虚拟通道在结构链路上有效地传送结构数据包。 VL可以具有不同的优先级，在该优先级下，较高优先级VL中的结构数据包的数据单元可以优先考虑低优先级VL中的结构数据包。通过传送数据单元而不是整个分组，可以临时暂停分组的传输，以利于较高优先级的分组。支持多种级别的抢占和嵌套方式的交错。

2. 发明授权

US06775339B1 Circuit design for high-speed digital communication 有权
标题翻译：电路设计用于高速数字通信
公开(公告)号：US06775339B1
公开(公告)日：2004-08-10
申请号：US09384906
申请日：1999-08-27
申请人： Paul T. Wildes , Mark S. Birrittella
发明人： Paul T. Wildes , Mark S. Birrittella
IPC分类号： H04L700
CPC分类号： G06F13/4243
摘要： The present invention provides a system for efficient, high speed, high bandwidth, digital communication where transmit distances are greater than a single clock period. The digital system operates based on a system clock. Within the digital system a transmit module transmits data along with a capture clock signal to a receive module where the transmission time between the modules is greater than one period of the system clock. The capture clock operates in a known relationship to the system clock at a frequency at least twice as slow as the system clock. The digital system also has a synchronizing clock that operates at the same frequency as the forwarded clock. When the data arrives at the receive module it is captured by a pair of memory devices operating on different phases of the capture clock. The memory devices feed the data to a multiplexor that selects, as a function of the synchronizing clock, between the outputs of the two memory devices. At this point the data has been synchronized with the system clock and can be captured using the system clock for processing in the receive module.
摘要翻译：本发明提供了一种用于有效，高速，高带宽的数字通信的系统，其中发射距离大于单个时钟周期。数字系统基于系统时钟进行操作。在数字系统中，发射模块将数据连同捕获时钟信号一起发送到接收模块，其中模块之间的传输时间大于系统时钟的一个周期。捕获时钟以系统时钟的至少两倍的频率与系统时钟以已知的关系运行。数字系统还具有与转发时钟频率相同的同步时钟。当数据到达接收模块时，它由在捕获时钟的不同相位上操作的一对存储器件捕获。存储器装置将数据馈送到多路器，多路复用器根据同步时钟在两个存储器件的输出之间进行选择。此时，数据已与系统时钟同步，并可使用系统时钟进行捕获，以便在接收模块中进行处理。

3. 发明授权

US5583990A System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel 失效
标题翻译：用于在虚拟通道之间分配消息以避免死锁并优化每种类型的虚拟通道上的消息流量的系统
公开(公告)号：US5583990A
公开(公告)日：1996-12-10
申请号：US165266
申请日：1993-12-10
申请人： Mark S. Birrittella , Richard E. Kessler , Steven M. Oberlin , Randal S. Passint , Greg Thorson
发明人： Mark S. Birrittella , Richard E. Kessler , Steven M. Oberlin , Randal S. Passint , Greg Thorson
IPC分类号： F16C39/06 , F16C32/04 , G06F15/16 , G06F15/173 , G06F15/80 , H04L12/56 , G06F13/00
CPC分类号： H04L45/06 , G06F15/17337 , G06F15/17381 , H04L45/10 , H04L49/101 , H04L49/205 , H04L49/251
摘要： A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.
摘要翻译：用于并行处理计算机的多维互连和路由设备将三维结构中的处理元件连接在一起。互连和路由设备包括多个处理单元节点。通信中的至少一个处理元件与主机系统连接。互连网络将处理元件节点连接在X，Y和Z维度上。该网络包括将多个处理元件中的每一个连接到X，Y和Z各维度的正负方向的相邻处理元件的通信路径。

4. 发明授权

US4628248A NPN bandgap voltage generator 失效
标题翻译： NPN带隙电压发生器
公开(公告)号：US4628248A
公开(公告)日：1986-12-09
申请号：US761207
申请日：1985-07-31
申请人： Mark S. Birrittella , Robert R. Marley , Keith D. Nootbaar
发明人： Mark S. Birrittella , Robert R. Marley , Keith D. Nootbaar
IPC分类号： G05F3/30 , G05F3/20
CPC分类号： G05F3/30 , Y10S323/907
摘要： An all NPN bandgap voltage reference is provided that includes a Widlar type temperature coefficient compensation circuit. A pair of NPN differentially connected transistors maintain a constant current in the Widlar circuit over variations in power supply voltage V.sub.EE while causing an increase in current in the Widlar circuit as temperature increases for maintaining a constant output voltage.
摘要翻译：提供了包括Widlar型温度系数补偿电路的全部NPN带隙电压基准。一对NPN差分连接的晶体管在Widlar电路中保持恒定的电流超过电源电压VEE的变化，同时当Widlar电路中的电流随着温度升高以维持恒定的输出电压而增加。

5. 发明授权

US07587305B2 Transistor level verilog 有权
标题翻译：晶体管级Verilog
公开(公告)号：US07587305B2
公开(公告)日：2009-09-08
申请号：US10180265
申请日：2002-06-26
申请人： Robert J. Lutz , Mark S. Birrittella , Eric C. Fromm , Harro Zimmermann
发明人： Robert J. Lutz , Mark S. Birrittella , Eric C. Fromm , Harro Zimmermann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a second leaf cell in Verilog syntax. A connection between the first leaf cell and the second leaf cell is also specified in Verilog syntax. This specifies a circuit. The functionality of the logic can be tested by running a logic simulation on the circuit without converting to Verilog syntax. The Verilog syntax, associated with the circuit, can be converted directly from Verilog syntax to a SPICE netlist. The SPICE netlist can be used to simulate the timing and other parameters of the circuit. The Verilog syntax can be used to verify the circuit. Also included are a computer readable medium including an instruction set for the above method, and a data structure necessary to carry out the above method.
摘要翻译：一种方法包括在Verilog语法中指定与第一叶单元相关联的第一组互连设备，以及在Verilog语法中指定与第二叶单元相关联的第二组互连设备。在Verilog语法中也指定了第一个叶单元和第二个叶单元之间的连接。这指定一个电路。可以通过在电路上运行逻辑仿真而不转换为Verilog语法来测试逻辑的功能。与电路相关的Verilog语法可以直接从Verilog语法转换为SPICE网表。 SPICE网表可用于模拟电路的时序和其他参数。 Verilog语法可用于验证电路。还包括包括用于上述方法的指令集的计算机可读介质，以及执行上述方法所需的数据结构。

6. 发明授权

US4649411A Gallium arsenide bipolar ECL circuit structure 失效
标题翻译：砷化镓双极ECL电路结构
公开(公告)号：US4649411A
公开(公告)日：1987-03-10
申请号：US682729
申请日：1984-12-17
申请人： Mark S. Birrittella
发明人： Mark S. Birrittella
IPC分类号： H01L27/06 , H01L29/732 , H01L29/72
CPC分类号： H01L29/732 , H01L27/0605
摘要： A gallium arsenide integrated circuit structure is disclosed wherein each transistor has only two of three terminals exposed at the semiconductor surface, thereby decreasing both the area of the structure and parasitic wiring capacitance. A dielectric buried layer overlies a portion of the substrate and isolates a first region from the remaining chip. This first region serves as common terminals of two or more transistors. Aluminum gallium arsenide is formed both above and below the base region for increasing the efficiency of the junction by eliminating the need for a heavily doped emitters, thereby allowing for symmetry of emitter and collector regions both on the semiconductor surface and below.
摘要翻译：公开了一种砷化镓集成电路结构，其中每个晶体管仅在半导体表面处露出三个端子中的两个，从而减小结构的面积和寄生布线电容。电介质掩埋层覆盖衬底的一部分，并将第一区与剩余芯片隔离。该第一区域用作两个或更多个晶体管的公共端子。在基极区域上方和下方形成砷化铝镓，以通过消除对重掺杂发射体的需要来提高结的效率，从而允许在半导体表面和下面的发射极和集电极区域的对称性。

7. 发明授权

US4635087A Monolithic bipolar SCR memory cell 失效
标题翻译：单片双极SCR存储单元
公开(公告)号：US4635087A
公开(公告)日：1987-01-06
申请号：US687530
申请日：1984-12-28
申请人： Mark S. Birrittella , Walter C. Seelbach
发明人： Mark S. Birrittella , Walter C. Seelbach
IPC分类号： G11C11/39 , G11C11/411 , H01L27/082 , H01L27/102 , H01L29/74 , G11C11/34 , H01L27/02 , H01L29/72
CPC分类号： H01L27/1025 , G11C11/39 , G11C11/4116 , H01L27/0826
摘要： Bipolar memory arrays having lower quiescent leakage and higher switching speed are constructed by using coupled SCRs formed from vertical PNP and NPN devices. Buried collectors for the PNP and NPN devices are provided within the same isolation tub. A P type plug is used to connect the P collector of the PNP to the P base of the NPN in a region where the P base and P collector overlap. A single N epi-region serves as the base of the PNP and the collector of the NPN. The P plug is located within this N epi-region but part of the N epi-region adjacent to or around the P plug is left so that internal connection of the PNP base and NPN collector is not cut off by the P plug. The structure is particularly suited for use in large memory arrays. The method of fabrication is also described.
摘要翻译：通过使用由垂直PNP和NPN器件形成的耦合SCR构成具有较低静态泄漏和较高开关速度的双极存储器阵列。 PNP和NPN设备的埋藏式收集器提供在同一隔离桶内。 P型插头用于在P基极和P集电极重叠的区域中将PNP的P集电极连接到NPN的P基极。单个N外延区域用作PNP的基极和NPN的收集器。 P插头位于该N外延区域内，但是与P插头相邻或附近的N外延区域的一部分保留，使得PNP基极和NPN集电极的内部连接不被P插头切断。该结构特别适用于大型存储器阵列。还描述了制造方法。

8. 发明授权

US5737628A Multiprocessor computer system with interleaved processing element nodes 失效
标题翻译：具有交错处理单元节点的多处理器计算机系统
公开(公告)号：US5737628A
公开(公告)日：1998-04-07
申请号：US662868
申请日：1996-06-12
申请人： Mark S. Birrittella , Richard E. Kessler , Steven M. Oberlin , Randal S. Passint , Greg Thorson
发明人： Mark S. Birrittella , Richard E. Kessler , Steven M. Oberlin , Randal S. Passint , Greg Thorson
IPC分类号： F16C39/06 , F16C32/04 , G06F15/16 , G06F15/173 , G06F15/80 , H04L12/56 , G06F15/76
CPC分类号： H04L45/06 , G06F15/17337 , G06F15/17381 , H04L45/10 , H04L49/101 , H04L49/205 , H04L49/251
摘要： A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.
摘要翻译：用于并行处理计算机的多维互连和路由设备将三维结构中的处理元件连接在一起。互连和路由设备包括多个处理单元节点。通信中的至少一个处理元件与主机系统连接。互连网络将处理元件节点连接在X，Y和Z维度上。该网络包括将多个处理元件中的每一个连接到X，Y和Z各维度的正负方向的相邻处理元件的通信路径。

9. 发明授权

US5182473A Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL) families 失效
标题翻译：发射极发射极逻辑（EEL）和发射极收集器虚线逻辑（ECDL）系列
公开(公告)号：US5182473A
公开(公告)日：1993-01-26
申请号：US826214
申请日：1992-01-22
申请人： Jan A. Wikstrom , Mark S. Birrittella , David Kiefer , Stephen B. Smetana , Vernon W. Swanson
发明人： Jan A. Wikstrom , Mark S. Birrittella , David Kiefer , Stephen B. Smetana , Vernon W. Swanson
IPC分类号： H03K19/018 , H03K19/0185 , H03K19/082 , H03K19/0952
CPC分类号： H03K19/0952 , H03K19/01812 , H03K19/018542 , H03K19/082
摘要： Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and make use of a wired logic function in order to effect two levels of logic without adding the propagation delay through another logic gate. These arrays of logic gates are coupled to drivers which restore logic levels and provide the necessary power for driving interconnect capacitances while consuming and dissipating a minimum of power in the process. Another logic circuit discloses an array of logic gates as inputs to another logic gate, the individual gates consisting of gallium arsenide components and having drivers built into the output stage of each gate.
摘要翻译：公开了由高速逻辑门阵列组成的逻辑单元单元，其输出端连接在一起并耦合到低功率驱动器。通过使用无增益的非常快速的逻辑门并利用有线逻辑功能实现高速和开关速率，以便在不增加另一个逻辑门的传播延迟的情况下实现两个逻辑电平。这些逻辑门阵列耦合到驱动器，驱动器可恢复逻辑电平，并为驱动互连电容提供必要的电源，同时消耗和耗散该过程中的最小功率。另一个逻辑电路公开了一个逻辑门阵列作为另一个逻辑门的输入，各个门由砷化镓组件组成，并具有内置于每个门的输出级的驱动器。

10. 发明授权

US4964081A READ-WHILE-WRITE RAM CELL 失效
公开(公告)号：US4964081A
公开(公告)日：1990-10-16
申请号：US393528
申请日：1989-08-11
申请人： Mark S. Birrittella , Jan A. Wikstrom
发明人： Mark S. Birrittella , Jan A. Wikstrom
IPC分类号： G11C8/16 , G11C11/411
CPC分类号： G11C8/16 , G11C11/4113
摘要： A READ-WHILE-WRITE current-mode logic RAM cell suitable for use in a RAM device having the ability to simultaneously write and read data.The RAM cell contains a bit-cell consisting of flip-flop configured transistors differentially connected to a constant current source, a multiple-emitter transistor network tied to each bit-cell load resistor which prevents the bit-cell from saturating, separate READ and WRITE data lines, and READ and WRITE buffer transistors having READ and WRITE control lines.
摘要翻译：适用于能够同时写入和读取数据的RAM设备中的READ-WHILE-WRITE电流模式逻辑RAM单元。 RAM单元包含一个位元组，该单元由差分连接到恒流源的触发器配置的晶体管组成，连接到每个位单元负载电阻的多发射极晶体管网络阻止位单元饱和，单独的读和写数据线以及具有READ和WRITE控制线的READ和WRITE缓冲晶体管。

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