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1. 发明授权

US5182473A Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL) families 失效
标题翻译：发射极发射极逻辑（EEL）和发射极收集器虚线逻辑（ECDL）系列
公开(公告)号：US5182473A
公开(公告)日：1993-01-26
申请号：US826214
申请日：1992-01-22
申请人： Jan A. Wikstrom , Mark S. Birrittella , David Kiefer , Stephen B. Smetana , Vernon W. Swanson
发明人： Jan A. Wikstrom , Mark S. Birrittella , David Kiefer , Stephen B. Smetana , Vernon W. Swanson
IPC分类号： H03K19/018 , H03K19/0185 , H03K19/082 , H03K19/0952
CPC分类号： H03K19/0952 , H03K19/01812 , H03K19/018542 , H03K19/082
摘要： Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and make use of a wired logic function in order to effect two levels of logic without adding the propagation delay through another logic gate. These arrays of logic gates are coupled to drivers which restore logic levels and provide the necessary power for driving interconnect capacitances while consuming and dissipating a minimum of power in the process. Another logic circuit discloses an array of logic gates as inputs to another logic gate, the individual gates consisting of gallium arsenide components and having drivers built into the output stage of each gate.
摘要翻译：公开了由高速逻辑门阵列组成的逻辑单元单元，其输出端连接在一起并耦合到低功率驱动器。通过使用无增益的非常快速的逻辑门并利用有线逻辑功能实现高速和开关速率，以便在不增加另一个逻辑门的传播延迟的情况下实现两个逻辑电平。这些逻辑门阵列耦合到驱动器，驱动器可恢复逻辑电平，并为驱动互连电容提供必要的电源，同时消耗和耗散该过程中的最小功率。另一个逻辑电路公开了一个逻辑门阵列作为另一个逻辑门的输入，各个门由砷化镓组件组成，并具有内置于每个门的输出级的驱动器。

2. 发明授权

US4964081A READ-WHILE-WRITE RAM CELL 失效
公开(公告)号：US4964081A
公开(公告)日：1990-10-16
申请号：US393528
申请日：1989-08-11
申请人： Mark S. Birrittella , Jan A. Wikstrom
发明人： Mark S. Birrittella , Jan A. Wikstrom
IPC分类号： G11C8/16 , G11C11/411
CPC分类号： G11C8/16 , G11C11/4113
摘要： A READ-WHILE-WRITE current-mode logic RAM cell suitable for use in a RAM device having the ability to simultaneously write and read data.The RAM cell contains a bit-cell consisting of flip-flop configured transistors differentially connected to a constant current source, a multiple-emitter transistor network tied to each bit-cell load resistor which prevents the bit-cell from saturating, separate READ and WRITE data lines, and READ and WRITE buffer transistors having READ and WRITE control lines.
摘要翻译：适用于能够同时写入和读取数据的RAM设备中的READ-WHILE-WRITE电流模式逻辑RAM单元。 RAM单元包含一个位元组，该单元由差分连接到恒流源的触发器配置的晶体管组成，连接到每个位单元负载电阻的多发射极晶体管网络阻止位单元饱和，单独的读和写数据线以及具有READ和WRITE控制线的READ和WRITE缓冲晶体管。

3. 发明授权

US07071736B2 Half-swing line precharge method and apparatus 有权
标题翻译：半摆线预充方法及装置
公开(公告)号：US07071736B2
公开(公告)日：2006-07-04
申请号：US10848690
申请日：2004-05-17
申请人： Jan A. Wikstrom
发明人： Jan A. Wikstrom
IPC分类号： H03K19/096 , H03K3/289
CPC分类号： H03K19/01728
摘要： A method and apparatus of precharging data and/or address lines each having a large number of loads to a voltage midway between high and low using a source-follower configuration, and optionally driving only one-half of the precharge circuit based on a previous logical value on the line being precharged. In some embodiments, a driver circuit drives an output node either high or low during a first phase of each clock cycle, and a precharge circuit then precharges the output node to an intermediate voltage during a second phase of the clock cycle in preparation for the following clock cycle. Some embodiments include source-follower configured FETs to precharge, wherein these FETs turn off once the output voltage reaches an intermediate value.
摘要翻译：一种使用源跟随器配置将每个具有大量负载的数据和/或地址线预充电到高电平和低电压之间的电压的方法和装置，并且可选地仅基于先前的逻辑来驱动预充电电路的一半在线上的价值被预先充电。在一些实施例中，驱动器电路在每个时钟周期的第一阶段期间驱动输出节点为高电平或低电平，并且预充电电路然后在时钟周期的第二阶段期间将输出节点预充电到中间电压，以准备以下时钟周期。一些实施例包括用于预充电的源极跟随器配置的FET，其中一旦输出电压达到中间值，这些FET就关闭。

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