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1. 发明授权

US5780204A Backside wafer polishing for improved photolithography 失效
标题翻译：用于改进光刻的背面晶片抛光
公开(公告)号：US5780204A
公开(公告)日：1998-07-14
申请号：US790886
申请日：1997-02-03
申请人： Tho Le La , Subramanian Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Early
发明人： Tho Le La , Subramanian Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Early
IPC分类号： G03F7/09 , H01L21/304 , G03C5/00 , G03F7/00
CPC分类号： H01L21/304 , G03F7/09
摘要： The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by polishing the wafer backside prior to photolithography. It was found that particles adhering to and/or scratches on the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Backside polishing, as by chemical-/mechanical polishing, removes such adhering particles and/or scratches, thereby improving photolithographic accuracy.
摘要翻译：通过在光刻之前抛光晶片背面，改善了光刻处理的精度，特别是在形成介电层中的小直径通孔和/或沟槽中的精度。发现由先前的处理步骤导致的在晶片背面附着和/或划痕的颗粒导致不精确的光刻处理，特别是在亚微米级。通过化学/机械抛光进行背面抛光可以去除这些粘附的颗粒和/或划痕，从而提高光刻精度。

2. 发明授权

US6136510A Doubled-sided wafer scrubbing for improved photolithography 失效
标题翻译：双面晶圆洗涤，用于改进光刻
公开(公告)号：US6136510A
公开(公告)日：2000-10-24
申请号：US800940
申请日：1997-02-13
申请人： Tho Le La , Subramanian N. Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Regina Early
发明人： Tho Le La , Subramanian N. Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Regina Early
IPC分类号： G03F7/16 , H01L21/306 , G03F7/00
CPC分类号： G03F7/16 , H01L21/02063
摘要： The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by double-sided scrubbing the wafer prior to photolithography. It was found that particles adhering to the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Double-sided wafer scrubbing removes such adhering particles, thereby improving photolithographic accuracy.
摘要翻译：通过在光刻之前双面擦洗晶片来改善光刻处理的精度，特别是在形成介电层中的小直径通孔和/或沟槽中的精度。发现由先前处理步骤导致的粘附到晶片背面的颗粒导致不精确的光刻处理，特别是在亚微米级。双面晶圆洗涤除去这些粘附颗粒，从而提高光刻精度。

3. 发明授权

US06639271B1 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 失效
标题翻译：用于双位氮化物存储器件的完全隔离的介电存储器单元结构及其制造方法
公开(公告)号：US06639271B1
公开(公告)日：2003-10-28
申请号：US10027253
申请日：2001-12-20
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L29792
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
摘要翻译：在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

4. 发明授权

US08691647B1 Memory devices containing a high-K dielectric layer 有权
标题翻译：包含高K电介质层的存储器件
公开(公告)号：US08691647B1
公开(公告)日：2014-04-08
申请号：US10927692
申请日：2004-08-27
申请人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
发明人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/7881
摘要： In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO2; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO2.
摘要翻译：在一个实施例中，公开了一种半导体器件。所述半导体器件形成在具有有源区的半导体衬底上，所述半导体器件包括：栅极电介质层，其设置在所述半导体衬底上，所述栅极电介质层具有至少两个具有至少一个具有电介质的子层的子层常数大于SiO2; 形成在所述栅介质层上的浮置栅极，限定插入在所述半导体衬底的有源区域内形成的源极和漏极之间的沟道; 形成在浮动栅极上方的控制栅极; 以及插入在所述浮置栅极和所述控制栅极之间的隔间介电层，所述栅极间介电层包括：形成在所述浮动栅极上的第一层; 形成在所述第一层上的第二层; 以及形成在第二层上的第三层，其中第一层，第二层和第三层中的每一层具有大于SiO 2的介电常数。

5. 发明授权

US07001807B1 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 有权
公开(公告)号：US07001807B1
公开(公告)日：2006-02-21
申请号：US10997345
申请日：2004-11-24
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/31
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/512 , H01L29/517 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

6. 发明授权

US06861307B2 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 有权
标题翻译：用于双位氮化物存储器件的完全隔离的介电存储器单元结构及其制造方法
公开(公告)号：US06861307B2
公开(公告)日：2005-03-01
申请号：US10631199
申请日：2003-07-31
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/28 , H01L29/51 , H01L29/792 , H01L21/8238
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
摘要翻译：在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

7. 发明授权

US06828199B2 Monos device having buried metal silicide bit line 有权
标题翻译：具有埋置金属硅化物位线的单体器件
公开(公告)号：US06828199B2
公开(公告)日：2004-12-07
申请号：US10022798
申请日：2001-12-20
申请人： Jusuke Ogura , Mark T. Ramsbey , Arvind Halliyal , Zoran Krivokapic , Minh Van Ngo , Nicholas H. Tripisas
发明人： Jusuke Ogura , Mark T. Ramsbey , Arvind Halliyal , Zoran Krivokapic , Minh Van Ngo , Nicholas H. Tripisas
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/743 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.
摘要翻译：用于制造该器件的MONOS器件和方法具有形成在衬底上的电荷捕获介电层，例如氧化物 - 氮化物 - 氧化物（ONO）层。通过ONO层和衬底产生凹陷。在凹部中形成金属硅化物位线，并且在金属硅化物的顶部上形成位线氧化物。在ONO层和位线氧化物之间形成字线，并且在字线的顶部提供低电阻硅化物。硅化物例如由激光热退火形成。

8. 发明授权

US06798002B1 Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming 有权
标题翻译：双用途抗反射涂层和闪存间隔器等双栅技术及成型方法
公开(公告)号：US06798002B1
公开(公告)日：2004-09-28
申请号：US09607675
申请日：2000-06-30
申请人： Robert B. Ogle, Jr. , Tuan D. Pham , Mark T. Ramsbey
发明人： Robert B. Ogle, Jr. , Tuan D. Pham , Mark T. Ramsbey
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： A dual gate semiconductor device, such as a flash memory semiconductor device, whose plurality of dual gate sidewall spacer structure is formed by a first and second anti-reflection fabrication process. The sidewall spacers of the dual transistor gate structures in the core memory region are left coated with the second anti-reflective coating material, after being used for gate patterning, to act as sidewall spacers for use in subsequent ion implant and salicidation fabrication steps. The second anti-reflective coating material is selected from a material group such as silicon oxynitride (SiON), silicon nitride (Si3N4), and silicon germanium (SiGe), or other anti-reflective coating material having optical properties and that are compatible with the subsequent implant and salicidation steps.
摘要翻译：诸如闪存半导体器件的双栅极半导体器件，其多个双栅极侧壁间隔结构通过第一和第二抗反射制造工艺形成。核心存储器区域中的双晶体管栅极结构的侧壁间隔物在用于栅极图案化之后被第二抗反射涂层材料涂覆以用作用于后续离子注入和盐化制造步骤的侧壁间隔物。第二抗反射涂层材料选自诸如氮氧化硅（SiON），氮化硅（Si 3 N 4）和硅锗（SiGe）的材料组或具有光学性质的其它抗反射涂层材料，并且与随后的植入和盐化步骤。

9. 发明授权

US06730564B1 Salicided gate for virtual ground arrays 有权
标题翻译：用于虚拟地面阵列的闸门
公开(公告)号：US06730564B1
公开(公告)日：2004-05-04
申请号：US10217821
申请日：2002-08-12
申请人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , Y10S438/954
摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
摘要翻译：本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。未图案化的层保护字线之间的基板不会变成水银。本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。

10. 发明授权

US06720133B1 Memory manufacturing process using disposable ARC for wordline formation 失效
标题翻译：使用一次性ARC进行字线形成的存储器制造过程
公开(公告)号：US06720133B1
公开(公告)日：2004-04-13
申请号：US10126280
申请日：2002-04-19
申请人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
IPC分类号： G03F700
CPC分类号： H01L27/11568 , H01L27/115 , Y10S430/151
摘要： A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.
摘要翻译：集成电路的制造方法包括在芯区域上的电荷捕获材料下方具有位线的半导体衬底和在周边区域上的栅极绝缘体材料。在覆盖周边区域的同时，在芯区域上沉积并图案化字线栅极材料，硬掩模和第一光致抗蚀剂。在去除第一光致抗蚀剂之后，从芯区域中的字线栅极材料形成字线。在外围区域上沉积并图案化抗反射涂层和第二光致抗蚀剂并覆盖芯区域。防反射涂层是可去除的，而不会损坏电荷捕获材料。在去除第二光致抗蚀剂和抗反射涂层之后，栅极由周边区域中的字线栅极材料形成，并且集成电路完成。

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