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1. 发明授权

US06350627B1 Interlevel dielectric thickness monitor for complex semiconductor chips 有权
标题翻译：复合半导体芯片的层间电介质厚度监测器
公开(公告)号：US06350627B1
公开(公告)日：2002-02-26
申请号：US09548741
申请日：2000-04-13
申请人： Tho Le La , John Jianshi Wang , Hao Fang
发明人： Tho Le La , John Jianshi Wang , Hao Fang
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L21/76801 , H01L22/12
摘要： A method of measuring the thickness of a dielectric layer above a plurality of structures of differing types within a semiconductor chip. The method comprises the steps of: forming a plurality of monitor boxes on a semiconductor chip such that each of said plurality of monitor boxes represents a structure type within the semiconductor chip and has substantially the same step height as one of a plurality of differing structure types; forming a dielectric layer over the semiconductor chip; and measuring a thickness of the dielectric layer above at least one of the plurality of monitor boxes, wherein said thickness represents a thickness of the dielectric layer above a structure of the structure type represented by the monitor box. Also disclosed is a semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a plurality of structures of differing types located on a surface within the semiconductor chip; and a plurality of monitor boxes, located on said surface within the semiconductor chip, upon which measurements of dielectric thickness can be made, wherein each of the plurality of monitor boxes represents a structure type within the semiconductor chip.
摘要翻译：一种在半导体芯片内测量不同类型的多个结构之上的电介质层的厚度的方法。该方法包括以下步骤：在半导体芯片上形成多个监视盒，使得所述多个监视盒中的每一个表示半导体芯片内的结构类型，并具有与多种不同结构类型之一基本相同的台阶高度 ; 在所述半导体芯片上形成介电层; 以及测量所述多个监视盒中的至少一个的所述电介质层的厚度，其中所述厚度表示所述电介质层的厚度，所述电介质层的厚度在由所述监视盒所表示的结构类型的结构之上。还公开了允许用于精确的电介质厚度测量。芯片包括：位于半导体芯片内的表面上的不同类型的多个结构; 以及位于半导体芯片内的所述表面上的多个监视器盒，可以在其上进行介电厚度的测量，其中多个监视盒中的每一个表示半导体芯片内的结构类型。

2. 发明授权

US06072191A Interlevel dielectric thickness monitor for complex semiconductor chips 失效
标题翻译：复合半导体芯片的层间电介质厚度监测器
公开(公告)号：US06072191A
公开(公告)日：2000-06-06
申请号：US991299
申请日：1997-12-16
申请人： Tho Le La , John Jianshi Wang , Hao Fang
发明人： Tho Le La , John Jianshi Wang , Hao Fang
IPC分类号： H01L21/66 , H01L21/768 , H01L23/544 , H01L23/58 , H01L21/4763
CPC分类号： H01L22/34 , H01L21/76801 , H01L22/12
摘要： A method of measuring the thickness of a dielectric layer above a plurality of structures of differing types within a semiconductor chip. The method comprises the steps of: forming a plurality of monitor boxes on a semiconductor chip such that each of said plurality of monitor boxes represents a structure type within the semiconductor chip and has substantially the same step height as one of a plurality of differing structure types; forming a dielectric layer over the semiconductor chip; and measuring a thickness of the dielectric layer above at least one of the plurality of monitor boxes, wherein said thickness represents a thickness of the dielectric layer above a structure of the structure type represented by the monitor box.Also disclosed is a semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a plurality of structures of differing types located on a surface within the semiconductor chip; and a plurality of monitor boxes, located on said surface within the semiconductor chip, upon which measurements of dielectric thickness can be made, wherein each of the plurality of monitor boxes represents a structure type within the semiconductor chip.
摘要翻译：一种在半导体芯片内测量不同类型的多个结构之上的电介质层的厚度的方法。该方法包括以下步骤：在半导体芯片上形成多个监视盒，使得所述多个监视盒中的每一个表示半导体芯片内的结构类型，并具有与多种不同结构类型之一基本相同的台阶高度 ; 在所述半导体芯片上形成介电层; 以及测量所述多个监视盒中的至少一个上的所述电介质层的厚度，其中所述厚度表示所述电介质层的厚度，所述电介质层在由所述监视盒所表示的结构类型的结构之上。还公开了允许精确的电介质厚度测量的半导体芯片。芯片包括：位于半导体芯片内的表面上的不同类型的多个结构; 以及位于半导体芯片内的所述表面上的多个监视器盒，可以在其上进行介电厚度的测量，其中多个监视盒中的每一个表示半导体芯片内的结构类型。

3. 发明授权

US5780204A Backside wafer polishing for improved photolithography 失效
标题翻译：用于改进光刻的背面晶片抛光
公开(公告)号：US5780204A
公开(公告)日：1998-07-14
申请号：US790886
申请日：1997-02-03
申请人： Tho Le La , Subramanian Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Early
发明人： Tho Le La , Subramanian Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Early
IPC分类号： G03F7/09 , H01L21/304 , G03C5/00 , G03F7/00
CPC分类号： H01L21/304 , G03F7/09
摘要： The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by polishing the wafer backside prior to photolithography. It was found that particles adhering to and/or scratches on the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Backside polishing, as by chemical-/mechanical polishing, removes such adhering particles and/or scratches, thereby improving photolithographic accuracy.
摘要翻译：通过在光刻之前抛光晶片背面，改善了光刻处理的精度，特别是在形成介电层中的小直径通孔和/或沟槽中的精度。发现由先前的处理步骤导致的在晶片背面附着和/或划痕的颗粒导致不精确的光刻处理，特别是在亚微米级。通过化学/机械抛光进行背面抛光可以去除这些粘附的颗粒和/或划痕，从而提高光刻精度。

4. 发明授权

US06507942B1 Methods and circuits for testing a circuit fabrication process for device uniformity 有权
标题翻译：用于测试器件均匀性的电路制造工艺的方法和电路
公开(公告)号：US06507942B1
公开(公告)日：2003-01-14
申请号：US09613494
申请日：2000-07-11
申请人： Anthony P. Calderone , Feng Wang , Tho Le La
发明人： Anthony P. Calderone , Feng Wang , Tho Le La
IPC分类号： G06F1750
CPC分类号： H01L22/34
摘要： Described are systems and methods for measuring the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process. An integrated circuit is configured to include a number of oscillators, each occupying a region of the integrated circuit. Each oscillator oscillates at a frequency that depends on the critical dimension of features in the region in which it is formed. Consequently, the critical dimensions of regions across the surface of the integrated circuit can be mapped and compared by comparing the oscillation frequencies of identical oscillators formed in various regions of the integrated circuit. In programmable logic devices, oscillators can be implemented using programmable logic resources. In other embodiments, small, simple oscillators can be placed at various locations on the integrated circuit.
摘要翻译：描述了用于测量由集成电路制造工艺的关键尺寸限定的电路特征的尺寸均匀性的系统和方法。集成电路被配置为包括多个振荡器，每个振荡器占据集成电路的一个区域。每个振荡器以取决于其形成区域中的特征的临界尺寸的频率振荡。因此，可以通过比较在集成电路的各个区域中形成的相同振荡器的振荡频率来映射和比较集成电路表面上的区域的临界尺寸。在可编程逻辑器件中，可以使用可编程逻辑资源实现振荡器。在其他实施例中，小的简单振荡器可以放置在集成电路上的各个位置。

5. 发明授权

US6136510A Doubled-sided wafer scrubbing for improved photolithography 失效
标题翻译：双面晶圆洗涤，用于改进光刻
公开(公告)号：US6136510A
公开(公告)日：2000-10-24
申请号：US800940
申请日：1997-02-13
申请人： Tho Le La , Subramanian N. Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Regina Early
发明人： Tho Le La , Subramanian N. Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Regina Early
IPC分类号： G03F7/16 , H01L21/306 , G03F7/00
CPC分类号： G03F7/16 , H01L21/02063
摘要： The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by double-sided scrubbing the wafer prior to photolithography. It was found that particles adhering to the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Double-sided wafer scrubbing removes such adhering particles, thereby improving photolithographic accuracy.
摘要翻译：通过在光刻之前双面擦洗晶片来改善光刻处理的精度，特别是在形成介电层中的小直径通孔和/或沟槽中的精度。发现由先前处理步骤导致的粘附到晶片背面的颗粒导致不精确的光刻处理，特别是在亚微米级。双面晶圆洗涤除去这些粘附颗粒，从而提高光刻精度。

6. 发明授权

US5761064A Defect management system for productivity and yield improvement 失效
标题翻译：缺陷管理系统提高生产率和产量
公开(公告)号：US5761064A
公开(公告)日：1998-06-02
申请号：US539913
申请日：1995-10-06
申请人： Tho Le La , Ying Shiau
发明人： Tho Le La , Ying Shiau
IPC分类号： G01R31/319 , H01L21/66 , G06F19/00
CPC分类号： H01L22/20 , G01R31/319
摘要： An automated wafer defect management system in which wafer defect data are collected from wafer inspection instruments, converted into a standard data format and made available through a central database system to workstations for review, analysis, and evaluation.
摘要翻译：一种自动晶片缺陷管理系统，其中晶圆缺陷数据从晶圆检测仪器采集，转换为标准数据格式，并通过中央数据库系统提供给工作站进行审查，分析和评估。

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